EDN Simulation Results

Sunday April 28 2024 19:02:25 UTC

GitHub Revision: `ae68723071`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 39039922970915743742128251849028328647614073777998354662703170901147801110391

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.100s	18.961us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.010s	22.919us	5	5	100.00
V1	csr_rw	edn_csr_rw	1.020s	17.022us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	6.290s	253.448us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.600s	43.548us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	2.010s	109.024us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.020s	17.022us	20	20	100.00
		edn_csr_aliasing	1.600s	43.548us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	3.288m	16.808ms	300	300	100.00
V2	csrng_commands	edn_genbits	3.288m	16.808ms	300	300	100.00
V2	genbits	edn_genbits	3.288m	16.808ms	300	300	100.00
V2	interrupts	edn_intr	1.250s	24.058us	50	50	100.00
V2	alerts	edn_alert	1.440s	29.532us	50	50	100.00
V2	errs	edn_err	1.530s	29.016us	100	100	100.00
V2	disable	edn_disable	1.010s	14.998us	50	50	100.00
		edn_disable_auto_req_mode	1.560s	431.345us	48	50	96.00
V2	stress_all	edn_stress_all	7.530s	672.910us	50	50	100.00
V2	intr_test	edn_intr_test	0.980s	31.603us	50	50	100.00
V2	alert_test	edn_alert_test	1.370s	35.766us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.590s	526.303us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.590s	526.303us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.010s	22.919us	5	5	100.00
		edn_csr_rw	1.020s	17.022us	20	20	100.00
		edn_csr_aliasing	1.600s	43.548us	5	5	100.00
		edn_same_csr_outstanding	1.440s	333.390us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.010s	22.919us	5	5	100.00
		edn_csr_rw	1.020s	17.022us	20	20	100.00
		edn_csr_aliasing	1.600s	43.548us	5	5	100.00
		edn_same_csr_outstanding	1.440s	333.390us	20	20	100.00
V2		TOTAL			788	790	99.75
V2S	tl_intg_err	edn_sec_cm	10.250s	601.712us	5	5	100.00
		edn_tl_intg_err	2.830s	246.083us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.090s	18.995us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.440s	29.532us	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	10.250s	601.712us	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	10.250s	601.712us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	10.250s	601.712us	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	10.250s	601.712us	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.440s	29.532us	50	50	100.00
		edn_sec_cm	10.250s	601.712us	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.440s	29.532us	50	50	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.830s	246.083us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	46.079m	118.820ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			978	980	99.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	10	90.91
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.24	98.24	93.76	97.01	81.50	96.76	99.77	92.64

Failure Buckets

UVM_ERROR (edn_scoreboard.sv:313) [scoreboard] Check failed sw_cmd_sts == item.d_data (* [*] vs * [*]) reg name: edn_reg_block.sw_cmd_sts has 2 failures:
- Test edn_disable_auto_req_mode has 2 failures.
  - 1.edn_disable_auto_req_mode.80948178119052762305892162559408123775731069816086752186028504987798904352201
    Line 261, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/1.edn_disable_auto_req_mode/latest/run.log
```
  UVM_ERROR @  71737629 ps: (edn_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (4 [0x4] vs 1 [0x1]) reg name: edn_reg_block.sw_cmd_sts
  UVM_INFO @  71737629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 31.edn_disable_auto_req_mode.107999167834270394659790193299731505084593701272811339214210725224251972033221
    Line 258, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/31.edn_disable_auto_req_mode/latest/run.log
```
  UVM_ERROR @   7076023 ps: (edn_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (0 [0x0] vs 1 [0x1]) reg name: edn_reg_block.sw_cmd_sts
  UVM_INFO @   7076023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

EDN Simulation Results

Sunday April 28 2024 19:02:25 UTC

GitHub Revision: ae68723071

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 39039922970915743742128251849028328647614073777998354662703170901147801110391

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `ae68723071`