EDN Simulation Results

Tuesday April 30 2024 19:02:27 UTC

GitHub Revision: `0cb61fc7e7`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29629349767786988748941369645310183062873507656225682712521573681396210883738

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.050s	18.165us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.150s	28.709us	5	5	100.00
V1	csr_rw	edn_csr_rw	1.050s	17.038us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	3.730s	571.741us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.470s	34.673us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	2.030s	52.416us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.050s	17.038us	20	20	100.00
		edn_csr_aliasing	1.470s	34.673us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	1.220m	2.199ms	300	300	100.00
V2	csrng_commands	edn_genbits	1.220m	2.199ms	300	300	100.00
V2	genbits	edn_genbits	1.220m	2.199ms	300	300	100.00
V2	interrupts	edn_intr	1.320s	21.711us	50	50	100.00
V2	alerts	edn_alert	1.380s	344.776us	50	50	100.00
V2	errs	edn_err	1.400s	36.842us	100	100	100.00
V2	disable	edn_disable	0.970s	14.461us	50	50	100.00
		edn_disable_auto_req_mode	1.390s	128.083us	47	50	94.00
V2	stress_all	edn_stress_all	6.920s	355.156us	50	50	100.00
V2	intr_test	edn_intr_test	0.990s	16.975us	50	50	100.00
V2	alert_test	edn_alert_test	2.080s	91.103us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	5.930s	1.522ms	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	5.930s	1.522ms	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.150s	28.709us	5	5	100.00
		edn_csr_rw	1.050s	17.038us	20	20	100.00
		edn_csr_aliasing	1.470s	34.673us	5	5	100.00
		edn_same_csr_outstanding	1.510s	51.272us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.150s	28.709us	5	5	100.00
		edn_csr_rw	1.050s	17.038us	20	20	100.00
		edn_csr_aliasing	1.470s	34.673us	5	5	100.00
		edn_same_csr_outstanding	1.510s	51.272us	20	20	100.00
V2		TOTAL			787	790	99.62
V2S	tl_intg_err	edn_sec_cm	8.510s	1.901ms	5	5	100.00
		edn_tl_intg_err	6.310s	351.908us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.090s	19.232us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.380s	344.776us	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	8.510s	1.901ms	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	8.510s	1.901ms	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	8.510s	1.901ms	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	8.510s	1.901ms	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.380s	344.776us	50	50	100.00
		edn_sec_cm	8.510s	1.901ms	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.380s	344.776us	50	50	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	6.310s	351.908us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	47.869m	354.372ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			977	980	99.69

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	10	90.91
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.33	98.24	93.76	97.06	82.08	96.76	99.77	92.64

Failure Buckets

UVM_ERROR (edn_scoreboard.sv:313) [scoreboard] Check failed sw_cmd_sts == item.d_data (* [*] vs * [*]) reg name: edn_reg_block.sw_cmd_sts has 2 failures:
- Test edn_disable_auto_req_mode has 2 failures.
  - 9.edn_disable_auto_req_mode.113864005810883926241070107894424044024389885675105968850833538133763712372441
    Line 261, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/9.edn_disable_auto_req_mode/latest/run.log
```
  UVM_ERROR @  20331528 ps: (edn_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (4 [0x4] vs 7 [0x7]) reg name: edn_reg_block.sw_cmd_sts
  UVM_INFO @  20331528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 18.edn_disable_auto_req_mode.38521994528122636147822229854530102766978525706353940627134841966245607886080
    Line 261, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/18.edn_disable_auto_req_mode/latest/run.log
```
  UVM_ERROR @  57541126 ps: (edn_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (4 [0x4] vs 7 [0x7]) reg name: edn_reg_block.sw_cmd_sts
  UVM_INFO @  57541126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test edn_disable_auto_req_mode has 1 failures.
  - 36.edn_disable_auto_req_mode.18075750001125941282311025659914178910290531295750835380435267428827313682334
    Line 258, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/36.edn_disable_auto_req_mode/latest/run.log
```
  UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

EDN Simulation Results

Tuesday April 30 2024 19:02:27 UTC

GitHub Revision: 0cb61fc7e7

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29629349767786988748941369645310183062873507656225682712521573681396210883738

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `0cb61fc7e7`