EDN Simulation Results

Thursday May 02 2024 19:03:09 UTC

GitHub Revision: ecd9f08747

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 19770536698299155636913061839112149222426010608929753156399703507865583879800

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.060s	18.664us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.000s	32.456us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.950s	54.595us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	5.350s	358.125us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.560s	78.561us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.760s	55.435us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.950s	54.595us	20	20	100.00
		edn_csr_aliasing	1.560s	78.561us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	7.750s	1.041ms	300	300	100.00
V2	csrng_commands	edn_genbits	7.750s	1.041ms	300	300	100.00
V2	genbits	edn_genbits	7.750s	1.041ms	300	300	100.00
V2	interrupts	edn_intr	1.330s	31.088us	50	50	100.00
V2	alerts	edn_alert	1.500s	364.515us	50	50	100.00
V2	errs	edn_err	1.500s	33.649us	100	100	100.00
V2	disable	edn_disable	2.550s	500.000us	49	50	98.00
		edn_disable_auto_req_mode	1.570s	46.942us	45	50	90.00
V2	stress_all	edn_stress_all	6.920s	355.340us	50	50	100.00
V2	intr_test	edn_intr_test	0.960s	18.954us	50	50	100.00
V2	alert_test	edn_alert_test	1.260s	39.287us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.740s	287.195us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.740s	287.195us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.000s	32.456us	5	5	100.00
		edn_csr_rw	0.950s	54.595us	20	20	100.00
		edn_csr_aliasing	1.560s	78.561us	5	5	100.00
		edn_same_csr_outstanding	1.410s	43.838us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.000s	32.456us	5	5	100.00
		edn_csr_rw	0.950s	54.595us	20	20	100.00
		edn_csr_aliasing	1.560s	78.561us	5	5	100.00
		edn_same_csr_outstanding	1.410s	43.838us	20	20	100.00
V2		TOTAL			784	790	99.24
V2S	tl_intg_err	edn_sec_cm	10.010s	993.047us	5	5	100.00
		edn_tl_intg_err	4.460s	229.052us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.060s	24.430us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.500s	364.515us	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	10.010s	993.047us	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	10.010s	993.047us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	10.010s	993.047us	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	10.010s	993.047us	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.500s	364.515us	50	50	100.00
		edn_sec_cm	10.010s	993.047us	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.500s	364.515us	50	50	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	4.460s	229.052us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	58.008m	1.161s	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			974	980	99.39

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	9	81.82
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.25	98.24	93.82	97.01	81.50	96.76	99.77	92.64

Failure Buckets

• UVM_ERROR (edn_scoreboard.sv:313) [scoreboard] Check failed sw_cmd_sts == item.d_data (* [*] vs * [*]) reg name: edn_reg_block.sw_cmd_sts has 4 failures:
  • Test edn_disable_auto_req_mode has 4 failures.

    • 6.edn_disable_auto_req_mode.77047494600138963452391323051803274180788051609673760615506566603459639504983
      Line 261, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/6.edn_disable_auto_req_mode/latest/run.log

        UVM_ERROR @  28281251 ps: (edn_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (4 [0x4] vs 7 [0x7]) reg name: edn_reg_block.sw_cmd_sts
        UVM_INFO @  28281251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 18.edn_disable_auto_req_mode.115622696143037252793693430671422652912197261042575522654731629751139569760319
      Line 258, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/18.edn_disable_auto_req_mode/latest/run.log

        UVM_ERROR @   9761306 ps: (edn_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (0 [0x0] vs 4 [0x4]) reg name: edn_reg_block.sw_cmd_sts
        UVM_INFO @   9761306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 2 more failures.

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:

  • Test edn_disable_auto_req_mode has 1 failures.

    • 11.edn_disable_auto_req_mode.113091685865762251443925952542591060710073346129181133657029896470391873622235
      Line 258, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/11.edn_disable_auto_req_mode/latest/run.log

        UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test edn_disable has 1 failures.

    • 13.edn_disable.11388121057759789915576591361730041168649766687217367024127396036992717525722
      Line 258, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/13.edn_disable/latest/run.log

        UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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