EDN Simulation Results

Sunday May 05 2024 19:05:13 UTC

GitHub Revision: `d0c52cdadd`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 81579111587980121648949789282063322266496016209500883225240730864920651071561

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.060s	16.066us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.930s	167.362us	5	5	100.00
V1	csr_rw	edn_csr_rw	1.020s	16.064us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	7.060s	4.930ms	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.620s	159.700us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	2.070s	33.903us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.020s	16.064us	20	20	100.00
		edn_csr_aliasing	1.620s	159.700us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	1.596m	9.565ms	300	300	100.00
V2	csrng_commands	edn_genbits	1.596m	9.565ms	300	300	100.00
V2	genbits	edn_genbits	1.596m	9.565ms	300	300	100.00
V2	interrupts	edn_intr	1.170s	23.544us	50	50	100.00
V2	alerts	edn_alert	1.540s	428.129us	50	50	100.00
V2	errs	edn_err	1.330s	28.715us	100	100	100.00
V2	disable	edn_disable	0.970s	12.856us	50	50	100.00
		edn_disable_auto_req_mode	1.580s	500.000us	46	50	92.00
V2	stress_all	edn_stress_all	7.410s	406.714us	50	50	100.00
V2	intr_test	edn_intr_test	1.050s	17.882us	50	50	100.00
V2	alert_test	edn_alert_test	1.140s	28.767us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.520s	507.606us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.520s	507.606us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.930s	167.362us	5	5	100.00
		edn_csr_rw	1.020s	16.064us	20	20	100.00
		edn_csr_aliasing	1.620s	159.700us	5	5	100.00
		edn_same_csr_outstanding	1.600s	150.201us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.930s	167.362us	5	5	100.00
		edn_csr_rw	1.020s	16.064us	20	20	100.00
		edn_csr_aliasing	1.620s	159.700us	5	5	100.00
		edn_same_csr_outstanding	1.600s	150.201us	20	20	100.00
V2		TOTAL			786	790	99.49
V2S	tl_intg_err	edn_sec_cm	9.400s	1.354ms	5	5	100.00
		edn_tl_intg_err	5.980s	329.732us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.970s	127.190us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.540s	428.129us	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	9.400s	1.354ms	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	9.400s	1.354ms	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	9.400s	1.354ms	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	9.400s	1.354ms	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.540s	428.129us	50	50	100.00
		edn_sec_cm	9.400s	1.354ms	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.540s	428.129us	50	50	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	5.980s	329.732us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	50.202m	424.458ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			976	980	99.59

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	10	90.91
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.30	98.24	93.76	97.02	82.08	96.76	99.77	92.47

Failure Buckets

UVM_ERROR (edn_scoreboard.sv:313) [scoreboard] Check failed sw_cmd_sts == item.d_data (* [*] vs * [*]) reg name: edn_reg_block.sw_cmd_sts has 3 failures:
- Test edn_disable_auto_req_mode has 3 failures.
  - 6.edn_disable_auto_req_mode.54433158439156122443312458540656012130830202329242750771247128625030336802488
    Line 261, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/6.edn_disable_auto_req_mode/latest/run.log
```
  UVM_ERROR @  35973176 ps: (edn_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (4 [0x4] vs 1 [0x1]) reg name: edn_reg_block.sw_cmd_sts
  UVM_INFO @  35973176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 10.edn_disable_auto_req_mode.76106345085541203773814943283308937613234134197133483527334937244815669084446
    Line 258, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/10.edn_disable_auto_req_mode/latest/run.log
```
  UVM_ERROR @  44379386 ps: (edn_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (0 [0x0] vs 4 [0x4]) reg name: edn_reg_block.sw_cmd_sts
  UVM_INFO @  44379386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test edn_disable_auto_req_mode has 1 failures.
  - 12.edn_disable_auto_req_mode.44412030687796523949340869666380015462952756630245332689889252858803260967095
    Line 258, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/12.edn_disable_auto_req_mode/latest/run.log
```
  UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

EDN Simulation Results

Sunday May 05 2024 19:05:13 UTC

GitHub Revision: d0c52cdadd

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 81579111587980121648949789282063322266496016209500883225240730864920651071561

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `d0c52cdadd`