EDN Simulation Results

Tuesday May 07 2024 19:02:25 UTC

GitHub Revision: `18c8953cf1`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 23463731882259624708557902606691160899163550314542713462365308032920382521803

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.080s	15.907us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.960s	44.789us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.930s	57.502us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	6.410s	1.249ms	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.560s	177.343us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.800s	27.001us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.930s	57.502us	20	20	100.00
		edn_csr_aliasing	1.560s	177.343us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	6.830s	824.484us	300	300	100.00
V2	csrng_commands	edn_genbits	6.830s	824.484us	300	300	100.00
V2	genbits	edn_genbits	6.830s	824.484us	300	300	100.00
V2	interrupts	edn_intr	1.270s	22.590us	50	50	100.00
V2	alerts	edn_alert	1.590s	506.654us	50	50	100.00
V2	errs	edn_err	1.400s	30.831us	100	100	100.00
V2	disable	edn_disable	0.960s	13.697us	50	50	100.00
		edn_disable_auto_req_mode	1.360s	41.858us	43	50	86.00
V2	stress_all	edn_stress_all	6.560s	660.822us	50	50	100.00
V2	intr_test	edn_intr_test	0.970s	16.568us	50	50	100.00
V2	alert_test	edn_alert_test	1.500s	48.362us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.560s	784.275us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.560s	784.275us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.960s	44.789us	5	5	100.00
		edn_csr_rw	0.930s	57.502us	20	20	100.00
		edn_csr_aliasing	1.560s	177.343us	5	5	100.00
		edn_same_csr_outstanding	1.390s	68.259us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.960s	44.789us	5	5	100.00
		edn_csr_rw	0.930s	57.502us	20	20	100.00
		edn_csr_aliasing	1.560s	177.343us	5	5	100.00
		edn_same_csr_outstanding	1.390s	68.259us	20	20	100.00
V2		TOTAL			783	790	99.11
V2S	tl_intg_err	edn_sec_cm	8.610s	598.006us	5	5	100.00
		edn_tl_intg_err	4.890s	451.616us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.070s	19.207us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.590s	506.654us	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	8.610s	598.006us	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	8.610s	598.006us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	8.610s	598.006us	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	8.610s	598.006us	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.590s	506.654us	50	50	100.00
		edn_sec_cm	8.610s	598.006us	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.590s	506.654us	50	50	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	4.890s	451.616us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	46.230m	1.687s	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			972	980	99.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	10	90.91
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.23	98.24	93.82	97.02	81.50	96.76	99.77	92.47

Failure Buckets

UVM_ERROR (edn_scoreboard.sv:313) [scoreboard] Check failed sw_cmd_sts == item.d_data (* [*] vs * [*]) reg name: edn_reg_block.sw_cmd_sts has 5 failures:
- Test edn_disable_auto_req_mode has 5 failures.
  - 6.edn_disable_auto_req_mode.54635960363502994891236303878656289593179612842902140820297527324390536592998
    Line 261, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/6.edn_disable_auto_req_mode/latest/run.log
```
  UVM_ERROR @  14521619 ps: (edn_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (4 [0x4] vs 7 [0x7]) reg name: edn_reg_block.sw_cmd_sts
  UVM_INFO @  14521619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 10.edn_disable_auto_req_mode.61791052265345630835016373859760196989315789441742181419748515595461722209263
    Line 261, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/10.edn_disable_auto_req_mode/latest/run.log
```
  UVM_ERROR @  27369395 ps: (edn_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (4 [0x4] vs 1 [0x1]) reg name: edn_reg_block.sw_cmd_sts
  UVM_INFO @  27369395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test edn_disable_auto_req_mode has 2 failures.
  - 7.edn_disable_auto_req_mode.103120553675631921414649109118219030996205115864446722104274332617430889183578
    Line 258, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/7.edn_disable_auto_req_mode/latest/run.log
```
  UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 27.edn_disable_auto_req_mode.110043011170713354672766420171478517877862411295382515950018431619910683830256
    Line 258, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/27.edn_disable_auto_req_mode/latest/run.log
```
  UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job edn-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test edn_stress_all_with_rand_reset has 1 failures.
  - 26.edn_stress_all_with_rand_reset.10995226953793296044646572499020579723010934678912116047263006945121476372472
    Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/26.edn_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:88ef84a4-a04b-42c8-9657-d6571e68c457
```

EDN Simulation Results

Tuesday May 07 2024 19:02:25 UTC

GitHub Revision: 18c8953cf1

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 23463731882259624708557902606691160899163550314542713462365308032920382521803

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `18c8953cf1`