EDN Simulation Results

Thursday May 09 2024 19:02:32 UTC

GitHub Revision: 9656691e03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 30170103562476460183108208532025718695603957360441815475011549460912256789439

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.070s 18.638us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.010s 267.390us 5 5 100.00
V1 csr_rw edn_csr_rw 0.990s 185.664us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 6.260s 224.583us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.520s 254.215us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.610s 72.033us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.990s 185.664us 20 20 100.00
edn_csr_aliasing 1.520s 254.215us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 5.130s 603.696us 300 300 100.00
V2 csrng_commands edn_genbits 5.130s 603.696us 300 300 100.00
V2 genbits edn_genbits 5.130s 603.696us 300 300 100.00
V2 interrupts edn_intr 1.280s 22.338us 50 50 100.00
V2 alerts edn_alert 1.530s 363.429us 50 50 100.00
V2 errs edn_err 1.480s 37.916us 100 100 100.00
V2 disable edn_disable 1.050s 14.716us 50 50 100.00
edn_disable_auto_req_mode 1.450s 62.275us 45 50 90.00
V2 stress_all edn_stress_all 5.990s 314.596us 50 50 100.00
V2 intr_test edn_intr_test 0.980s 17.686us 50 50 100.00
V2 alert_test edn_alert_test 1.110s 87.085us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.060s 422.624us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.060s 422.624us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.010s 267.390us 5 5 100.00
edn_csr_rw 0.990s 185.664us 20 20 100.00
edn_csr_aliasing 1.520s 254.215us 5 5 100.00
edn_same_csr_outstanding 1.490s 73.226us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.010s 267.390us 5 5 100.00
edn_csr_rw 0.990s 185.664us 20 20 100.00
edn_csr_aliasing 1.520s 254.215us 5 5 100.00
edn_same_csr_outstanding 1.490s 73.226us 20 20 100.00
V2 TOTAL 785 790 99.37
V2S tl_intg_err edn_sec_cm 8.270s 532.489us 5 5 100.00
edn_tl_intg_err 3.420s 468.627us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 0.980s 28.720us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.530s 363.429us 50 50 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 8.270s 532.489us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 8.270s 532.489us 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 8.270s 532.489us 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 8.270s 532.489us 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.530s 363.429us 50 50 100.00
edn_sec_cm 8.270s 532.489us 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.530s 363.429us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 3.420s 468.627us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 51.127m 254.244ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 975 980 99.49

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 10 90.91
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
94.31 98.24 93.82 97.02 82.08 96.76 99.77 92.47

Failure Buckets

Past Results