EDN Simulation Results

Sunday May 12 2024 19:02:35 UTC

GitHub Revision: `69c572b503`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 72674276607041733394622960695970595070180537542023880499199659375034056632550

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.100s	18.360us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.990s	58.817us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.950s	15.425us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	5.780s	232.161us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.590s	66.495us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.970s	28.818us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.950s	15.425us	20	20	100.00
		edn_csr_aliasing	1.590s	66.495us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	1.466m	6.614ms	300	300	100.00
V2	csrng_commands	edn_genbits	1.466m	6.614ms	300	300	100.00
V2	genbits	edn_genbits	1.466m	6.614ms	300	300	100.00
V2	interrupts	edn_intr	1.220s	20.853us	50	50	100.00
V2	alerts	edn_alert	1.540s	331.762us	50	50	100.00
V2	errs	edn_err	1.400s	28.714us	100	100	100.00
V2	disable	edn_disable	5.830s	500.000us	49	50	98.00
		edn_disable_auto_req_mode	1.510s	50.686us	50	50	100.00
V2	stress_all	edn_stress_all	6.910s	353.800us	50	50	100.00
V2	intr_test	edn_intr_test	0.970s	15.117us	50	50	100.00
V2	alert_test	edn_alert_test	1.360s	79.402us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.570s	130.139us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.570s	130.139us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.990s	58.817us	5	5	100.00
		edn_csr_rw	0.950s	15.425us	20	20	100.00
		edn_csr_aliasing	1.590s	66.495us	5	5	100.00
		edn_same_csr_outstanding	1.380s	36.938us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.990s	58.817us	5	5	100.00
		edn_csr_rw	0.950s	15.425us	20	20	100.00
		edn_csr_aliasing	1.590s	66.495us	5	5	100.00
		edn_same_csr_outstanding	1.380s	36.938us	20	20	100.00
V2		TOTAL			789	790	99.87
V2S	tl_intg_err	edn_sec_cm	17.410s	1.130ms	5	5	100.00
		edn_tl_intg_err	3.120s	151.318us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.020s	31.112us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.540s	331.762us	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	17.410s	1.130ms	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	17.410s	1.130ms	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	17.410s	1.130ms	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	17.410s	1.130ms	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.540s	331.762us	50	50	100.00
		edn_sec_cm	17.410s	1.130ms	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.540s	331.762us	50	50	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	3.120s	151.318us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	46.543m	124.961ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			979	980	99.90

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	10	90.91
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.12	98.24	93.82	97.07	80.92	96.76	99.77	92.28

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test edn_disable has 1 failures.
  - 14.edn_disable.7392116615779382546059315445383438558827907166569332154296142561806348856997
    Line 258, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/14.edn_disable/latest/run.log
```
  UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

EDN Simulation Results

Sunday May 12 2024 19:02:35 UTC

GitHub Revision: 69c572b503

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 72674276607041733394622960695970595070180537542023880499199659375034056632550

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `69c572b503`