EDN Simulation Results

Tuesday May 14 2024 19:02:33 UTC

GitHub Revision: 00fe426038

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56275124637035941820967954627144971699378360917446801543187025394370981034792

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.170s 20.833us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.090s 23.972us 5 5 100.00
V1 csr_rw edn_csr_rw 0.980s 16.850us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 3.790s 134.323us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.520s 64.366us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.700s 24.102us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.980s 16.850us 20 20 100.00
edn_csr_aliasing 1.520s 64.366us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 1.240m 2.258ms 300 300 100.00
V2 csrng_commands edn_genbits 1.240m 2.258ms 300 300 100.00
V2 genbits edn_genbits 1.240m 2.258ms 300 300 100.00
V2 interrupts edn_intr 1.270s 26.238us 50 50 100.00
V2 alerts edn_alert 1.490s 348.093us 50 50 100.00
V2 errs edn_err 1.440s 32.718us 100 100 100.00
V2 disable edn_disable 0.980s 16.215us 50 50 100.00
edn_disable_auto_req_mode 1.670s 36.204us 50 50 100.00
V2 stress_all edn_stress_all 7.500s 377.118us 50 50 100.00
V2 intr_test edn_intr_test 0.980s 16.784us 50 50 100.00
V2 alert_test edn_alert_test 1.360s 44.092us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 5.600s 177.892us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 5.600s 177.892us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.090s 23.972us 5 5 100.00
edn_csr_rw 0.980s 16.850us 20 20 100.00
edn_csr_aliasing 1.520s 64.366us 5 5 100.00
edn_same_csr_outstanding 1.520s 377.828us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.090s 23.972us 5 5 100.00
edn_csr_rw 0.980s 16.850us 20 20 100.00
edn_csr_aliasing 1.520s 64.366us 5 5 100.00
edn_same_csr_outstanding 1.520s 377.828us 20 20 100.00
V2 TOTAL 790 790 100.00
V2S tl_intg_err edn_sec_cm 8.510s 951.089us 5 5 100.00
edn_tl_intg_err 2.790s 104.820us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.070s 20.060us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.490s 348.093us 50 50 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 8.510s 951.089us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 8.510s 951.089us 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 8.510s 951.089us 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 8.510s 951.089us 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.490s 348.093us 50 50 100.00
edn_sec_cm 8.510s 951.089us 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.490s 348.093us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 2.790s 104.820us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 42.950m 446.546ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 980 980 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
94.33 98.24 93.80 97.02 83.72 96.62 99.77 91.12

Past Results