EDN Simulation Results

Thursday May 16 2024 19:02:11 UTC

GitHub Revision: 349bab6601

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 60729333463373082946889975499553948547086354767408862399987151421185145065082

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.130s 16.062us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.980s 52.211us 5 5 100.00
V1 csr_rw edn_csr_rw 0.960s 14.938us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 6.500s 262.927us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.630s 270.218us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.080s 79.748us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.960s 14.938us 20 20 100.00
edn_csr_aliasing 1.630s 270.218us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 6.260s 711.292us 300 300 100.00
V2 csrng_commands edn_genbits 6.260s 711.292us 300 300 100.00
V2 genbits edn_genbits 6.260s 711.292us 300 300 100.00
V2 interrupts edn_intr 1.230s 21.312us 50 50 100.00
V2 alerts edn_alert 1.410s 33.278us 50 50 100.00
V2 errs edn_err 1.430s 32.286us 100 100 100.00
V2 disable edn_disable 0.970s 64.840us 50 50 100.00
edn_disable_auto_req_mode 1.410s 305.939us 50 50 100.00
V2 stress_all edn_stress_all 7.990s 430.341us 50 50 100.00
V2 intr_test edn_intr_test 0.950s 29.014us 50 50 100.00
V2 alert_test edn_alert_test 1.770s 142.237us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.850s 530.150us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.850s 530.150us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.980s 52.211us 5 5 100.00
edn_csr_rw 0.960s 14.938us 20 20 100.00
edn_csr_aliasing 1.630s 270.218us 5 5 100.00
edn_same_csr_outstanding 1.470s 33.839us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.980s 52.211us 5 5 100.00
edn_csr_rw 0.960s 14.938us 20 20 100.00
edn_csr_aliasing 1.630s 270.218us 5 5 100.00
edn_same_csr_outstanding 1.470s 33.839us 20 20 100.00
V2 TOTAL 790 790 100.00
V2S tl_intg_err edn_sec_cm 8.230s 4.569ms 5 5 100.00
edn_tl_intg_err 2.760s 268.584us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.060s 18.932us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.410s 33.278us 50 50 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 8.230s 4.569ms 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 8.230s 4.569ms 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 8.230s 4.569ms 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 8.230s 4.569ms 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.410s 33.278us 50 50 100.00
edn_sec_cm 8.230s 4.569ms 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.410s 33.278us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 2.760s 268.584us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 42.257m 106.848ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 980 980 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
94.33 98.24 93.80 97.02 83.72 96.62 99.77 91.12

Past Results