EDN Simulation Results

Sunday May 19 2024 19:02:23 UTC

GitHub Revision: eb776817a5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56458776725427632834749451790671712939002859133119076946547796163671543192855

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.130s 18.068us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.950s 26.909us 5 5 100.00
V1 csr_rw edn_csr_rw 1.000s 29.281us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 6.500s 1.262ms 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.430s 114.829us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.590s 27.625us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.000s 29.281us 20 20 100.00
edn_csr_aliasing 1.430s 114.829us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 6.730s 947.052us 300 300 100.00
V2 csrng_commands edn_genbits 6.730s 947.052us 300 300 100.00
V2 genbits edn_genbits 6.730s 947.052us 300 300 100.00
V2 interrupts edn_intr 1.290s 23.816us 50 50 100.00
V2 alerts edn_alert 1.540s 292.751us 50 50 100.00
V2 errs edn_err 1.470s 36.937us 100 100 100.00
V2 disable edn_disable 1.020s 12.172us 50 50 100.00
edn_disable_auto_req_mode 1.570s 52.878us 50 50 100.00
V2 stress_all edn_stress_all 6.740s 367.034us 50 50 100.00
V2 intr_test edn_intr_test 0.990s 15.056us 50 50 100.00
V2 alert_test edn_alert_test 1.220s 129.669us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.990s 296.420us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.990s 296.420us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.950s 26.909us 5 5 100.00
edn_csr_rw 1.000s 29.281us 20 20 100.00
edn_csr_aliasing 1.430s 114.829us 5 5 100.00
edn_same_csr_outstanding 1.580s 309.091us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.950s 26.909us 5 5 100.00
edn_csr_rw 1.000s 29.281us 20 20 100.00
edn_csr_aliasing 1.430s 114.829us 5 5 100.00
edn_same_csr_outstanding 1.580s 309.091us 20 20 100.00
V2 TOTAL 790 790 100.00
V2S tl_intg_err edn_sec_cm 8.070s 2.402ms 5 5 100.00
edn_tl_intg_err 7.720s 506.721us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.080s 31.485us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.540s 292.751us 50 50 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 8.070s 2.402ms 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 8.070s 2.402ms 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 8.070s 2.402ms 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 8.070s 2.402ms 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.540s 292.751us 50 50 100.00
edn_sec_cm 8.070s 2.402ms 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.540s 292.751us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 7.720s 506.721us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 47.498m 106.847ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 980 980 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
94.66 98.24 93.80 97.02 86.05 96.62 99.77 91.12

Past Results