EDN Simulation Results

Tuesday May 21 2024 19:02:35 UTC

GitHub Revision: be3d980075

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85829748320245376283659198434338498577935164172956485671224275001047693479661

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.090s	19.128us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.000s	31.867us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.990s	52.895us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	5.200s	346.109us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.420s	123.183us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.630s	95.173us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.990s	52.895us	20	20	100.00
		edn_csr_aliasing	1.420s	123.183us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	2.132m	9.125ms	300	300	100.00
V2	csrng_commands	edn_genbits	2.132m	9.125ms	300	300	100.00
V2	genbits	edn_genbits	2.132m	9.125ms	300	300	100.00
V2	interrupts	edn_intr	1.240s	29.456us	50	50	100.00
V2	alerts	edn_alert	1.360s	32.089us	50	50	100.00
V2	errs	edn_err	1.350s	40.754us	100	100	100.00
V2	disable	edn_disable	6.490s	500.000us	49	50	98.00
		edn_disable_auto_req_mode	1.590s	54.641us	50	50	100.00
V2	stress_all	edn_stress_all	6.720s	328.499us	50	50	100.00
V2	intr_test	edn_intr_test	1.000s	20.129us	50	50	100.00
V2	alert_test	edn_alert_test	1.140s	31.309us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.310s	103.066us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.310s	103.066us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.000s	31.867us	5	5	100.00
		edn_csr_rw	0.990s	52.895us	20	20	100.00
		edn_csr_aliasing	1.420s	123.183us	5	5	100.00
		edn_same_csr_outstanding	1.460s	33.356us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.000s	31.867us	5	5	100.00
		edn_csr_rw	0.990s	52.895us	20	20	100.00
		edn_csr_aliasing	1.420s	123.183us	5	5	100.00
		edn_same_csr_outstanding	1.460s	33.356us	20	20	100.00
V2		TOTAL			789	790	99.87
V2S	tl_intg_err	edn_sec_cm	10.410s	2.539ms	5	5	100.00
		edn_tl_intg_err	2.580s	258.160us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.070s	14.839us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.360s	32.089us	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	10.410s	2.539ms	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	10.410s	2.539ms	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	10.410s	2.539ms	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	10.410s	2.539ms	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.360s	32.089us	50	50	100.00
		edn_sec_cm	10.410s	2.539ms	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.360s	32.089us	50	50	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.580s	258.160us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	1.046h	344.728ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			979	980	99.90

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	10	90.91
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.58	98.24	93.80	97.02	85.47	96.62	99.77	91.12

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test edn_disable has 1 failures.

    • 6.edn_disable.48730318268422712420505363258931179184391931927490435730215624891521029116504
      Line 258, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/6.edn_disable/latest/run.log

        UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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