EDN Simulation Results

Thursday May 23 2024 19:02:32 UTC

GitHub Revision: 1579f6a912

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107680075914347604077716278187232582575581754843183664337576824686885697334979

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.110s 18.818us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.960s 24.344us 5 5 100.00
V1 csr_rw edn_csr_rw 0.960s 16.918us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 6.360s 259.585us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.620s 152.339us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.670s 213.236us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.960s 16.918us 20 20 100.00
edn_csr_aliasing 1.620s 152.339us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 5.790s 756.741us 300 300 100.00
V2 csrng_commands edn_genbits 5.790s 756.741us 300 300 100.00
V2 genbits edn_genbits 5.790s 756.741us 300 300 100.00
V2 interrupts edn_intr 1.250s 21.752us 50 50 100.00
V2 alerts edn_alert 1.370s 52.300us 50 50 100.00
V2 errs edn_err 1.370s 54.118us 100 100 100.00
V2 disable edn_disable 1.070s 11.736us 50 50 100.00
edn_disable_auto_req_mode 1.380s 139.566us 50 50 100.00
V2 stress_all edn_stress_all 7.560s 589.758us 50 50 100.00
V2 intr_test edn_intr_test 0.990s 14.989us 50 50 100.00
V2 alert_test edn_alert_test 1.770s 73.510us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.600s 147.016us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.600s 147.016us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.960s 24.344us 5 5 100.00
edn_csr_rw 0.960s 16.918us 20 20 100.00
edn_csr_aliasing 1.620s 152.339us 5 5 100.00
edn_same_csr_outstanding 1.450s 34.522us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.960s 24.344us 5 5 100.00
edn_csr_rw 0.960s 16.918us 20 20 100.00
edn_csr_aliasing 1.620s 152.339us 5 5 100.00
edn_same_csr_outstanding 1.450s 34.522us 20 20 100.00
V2 TOTAL 790 790 100.00
V2S tl_intg_err edn_sec_cm 8.100s 3.245ms 5 5 100.00
edn_tl_intg_err 9.940s 1.250ms 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.030s 23.199us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.370s 52.300us 50 50 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 8.100s 3.245ms 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 8.100s 3.245ms 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 8.100s 3.245ms 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 8.100s 3.245ms 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.370s 52.300us 50 50 100.00
edn_sec_cm 8.100s 3.245ms 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.370s 52.300us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 9.940s 1.250ms 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 38.607m 102.016ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 980 980 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
94.41 98.24 93.80 97.02 84.30 96.62 99.77 91.12

Past Results