EDN Simulation Results

Sunday May 26 2024 19:04:10 UTC

GitHub Revision: 2cf28c40e5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 76231542290686940289653487239061276463019235878731279188279352215076078972419

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.050s 15.294us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.020s 41.310us 5 5 100.00
V1 csr_rw edn_csr_rw 1.070s 16.069us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 7.190s 3.560ms 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.290s 27.475us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.990s 40.751us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.070s 16.069us 20 20 100.00
edn_csr_aliasing 1.290s 27.475us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 2.060m 8.744ms 300 300 100.00
V2 csrng_commands edn_genbits 2.060m 8.744ms 300 300 100.00
V2 genbits edn_genbits 2.060m 8.744ms 300 300 100.00
V2 interrupts edn_intr 1.240s 20.253us 50 50 100.00
V2 alerts edn_alert 1.530s 42.989us 50 50 100.00
V2 errs edn_err 1.410s 30.633us 100 100 100.00
V2 disable edn_disable 0.980s 10.685us 50 50 100.00
edn_disable_auto_req_mode 1.580s 50.586us 50 50 100.00
V2 stress_all edn_stress_all 7.320s 416.232us 50 50 100.00
V2 intr_test edn_intr_test 0.970s 16.387us 50 50 100.00
V2 alert_test edn_alert_test 1.420s 52.769us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.260s 130.942us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.260s 130.942us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.020s 41.310us 5 5 100.00
edn_csr_rw 1.070s 16.069us 20 20 100.00
edn_csr_aliasing 1.290s 27.475us 5 5 100.00
edn_same_csr_outstanding 1.490s 36.749us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.020s 41.310us 5 5 100.00
edn_csr_rw 1.070s 16.069us 20 20 100.00
edn_csr_aliasing 1.290s 27.475us 5 5 100.00
edn_same_csr_outstanding 1.490s 36.749us 20 20 100.00
V2 TOTAL 790 790 100.00
V2S tl_intg_err edn_sec_cm 7.330s 875.480us 5 5 100.00
edn_tl_intg_err 7.880s 438.922us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.110s 19.420us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.530s 42.989us 50 50 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 7.330s 875.480us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 7.330s 875.480us 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 7.330s 875.480us 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 7.330s 875.480us 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.530s 42.989us 50 50 100.00
edn_sec_cm 7.330s 875.480us 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.530s 42.989us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 7.880s 438.922us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 38.631m 406.547ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 980 980 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
94.57 98.24 93.74 97.02 85.47 96.62 99.77 91.12

Past Results