EDN Simulation Results

Tuesday May 28 2024 19:30:06 UTC

GitHub Revision: 0e5093d709

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 51604449886868634540233838791789448907774502353938218657919214072353062987195

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.090s 17.665us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.030s 20.354us 5 5 100.00
V1 csr_rw edn_csr_rw 1.000s 30.961us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 5.410s 176.268us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.280s 19.135us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.090s 221.130us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.000s 30.961us 20 20 100.00
edn_csr_aliasing 1.280s 19.135us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 7.720s 979.006us 300 300 100.00
V2 csrng_commands edn_genbits 7.720s 979.006us 300 300 100.00
V2 genbits edn_genbits 7.720s 979.006us 300 300 100.00
V2 interrupts edn_intr 1.270s 22.600us 50 50 100.00
V2 alerts edn_alert 1.570s 283.135us 50 50 100.00
V2 errs edn_err 1.400s 35.561us 100 100 100.00
V2 disable edn_disable 0.960s 14.168us 50 50 100.00
edn_disable_auto_req_mode 1.640s 59.381us 50 50 100.00
V2 stress_all edn_stress_all 6.330s 328.439us 50 50 100.00
V2 intr_test edn_intr_test 0.940s 15.055us 50 50 100.00
V2 alert_test edn_alert_test 1.080s 21.025us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.060s 101.465us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.060s 101.465us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.030s 20.354us 5 5 100.00
edn_csr_rw 1.000s 30.961us 20 20 100.00
edn_csr_aliasing 1.280s 19.135us 5 5 100.00
edn_same_csr_outstanding 1.570s 63.956us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.030s 20.354us 5 5 100.00
edn_csr_rw 1.000s 30.961us 20 20 100.00
edn_csr_aliasing 1.280s 19.135us 5 5 100.00
edn_same_csr_outstanding 1.570s 63.956us 20 20 100.00
V2 TOTAL 790 790 100.00
V2S tl_intg_err edn_sec_cm 8.500s 1.106ms 5 5 100.00
edn_tl_intg_err 3.430s 146.817us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.040s 17.850us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.570s 283.135us 50 50 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 8.500s 1.106ms 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 8.500s 1.106ms 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 8.500s 1.106ms 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 8.500s 1.106ms 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.570s 283.135us 50 50 100.00
edn_sec_cm 8.500s 1.106ms 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.570s 283.135us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 3.430s 146.817us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 59.509m 262.678ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 980 980 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
94.42 98.24 93.80 97.07 84.30 96.62 99.77 91.12

Past Results