EDN Simulation Results

Thursday May 30 2024 19:02:59 UTC

GitHub Revision: 8cb25a6867

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 26638040090898561482658723926798947801831709189350919955228328310045202344042

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.110s	23.805us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.950s	36.039us	5	5	100.00
V1	csr_rw	edn_csr_rw	1.010s	18.365us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	6.540s	1.084ms	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.590s	33.908us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.950s	29.442us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.010s	18.365us	20	20	100.00
		edn_csr_aliasing	1.590s	33.908us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	1.969m	8.722ms	300	300	100.00
V2	csrng_commands	edn_genbits	1.969m	8.722ms	300	300	100.00
V2	genbits	edn_genbits	1.969m	8.722ms	300	300	100.00
V2	interrupts	edn_intr	1.250s	21.451us	50	50	100.00
V2	alerts	edn_alert	1.490s	259.258us	50	50	100.00
V2	errs	edn_err	1.410s	29.508us	100	100	100.00
V2	disable	edn_disable	0.950s	17.108us	50	50	100.00
		edn_disable_auto_req_mode	1.630s	53.532us	50	50	100.00
V2	stress_all	edn_stress_all	7.270s	404.035us	50	50	100.00
V2	intr_test	edn_intr_test	0.950s	20.231us	50	50	100.00
V2	alert_test	edn_alert_test	1.100s	24.569us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	5.290s	155.964us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	5.290s	155.964us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.950s	36.039us	5	5	100.00
		edn_csr_rw	1.010s	18.365us	20	20	100.00
		edn_csr_aliasing	1.590s	33.908us	5	5	100.00
		edn_same_csr_outstanding	1.440s	36.667us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.950s	36.039us	5	5	100.00
		edn_csr_rw	1.010s	18.365us	20	20	100.00
		edn_csr_aliasing	1.590s	33.908us	5	5	100.00
		edn_same_csr_outstanding	1.440s	36.667us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	tl_intg_err	edn_sec_cm	7.780s	1.693ms	5	5	100.00
		edn_tl_intg_err	2.680s	113.673us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.060s	20.635us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.490s	259.258us	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	7.780s	1.693ms	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	7.780s	1.693ms	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	7.780s	1.693ms	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	7.780s	1.693ms	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.490s	259.258us	50	50	100.00
		edn_sec_cm	7.780s	1.693ms	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.490s	259.258us	50	50	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.680s	113.673us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	37.688m	411.461ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			980	980	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.52	98.24	93.80	97.02	84.88	96.62	99.77	91.31

Past Results

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