EDN Simulation Results

Sunday June 02 2024 19:02:53 UTC

GitHub Revision: 01a208901a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 50418669159766293903157726892781832882154091083197082086235277423705989875584

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.070s 18.728us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.910s 122.862us 5 5 100.00
V1 csr_rw edn_csr_rw 1.010s 17.211us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 6.470s 2.757ms 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.520s 78.352us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.090s 61.636us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.010s 17.211us 20 20 100.00
edn_csr_aliasing 1.520s 78.352us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 1.194m 2.289ms 300 300 100.00
V2 csrng_commands edn_genbits 1.194m 2.289ms 300 300 100.00
V2 genbits edn_genbits 1.194m 2.289ms 300 300 100.00
V2 interrupts edn_intr 1.270s 23.630us 50 50 100.00
V2 alerts edn_alert 1.360s 191.804us 50 50 100.00
V2 errs edn_err 1.380s 55.815us 100 100 100.00
V2 disable edn_disable 0.950s 11.061us 50 50 100.00
edn_disable_auto_req_mode 1.660s 50.322us 50 50 100.00
V2 stress_all edn_stress_all 6.330s 530.025us 50 50 100.00
V2 intr_test edn_intr_test 0.990s 60.493us 50 50 100.00
V2 alert_test edn_alert_test 1.070s 27.172us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.430s 478.845us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.430s 478.845us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.910s 122.862us 5 5 100.00
edn_csr_rw 1.010s 17.211us 20 20 100.00
edn_csr_aliasing 1.520s 78.352us 5 5 100.00
edn_same_csr_outstanding 1.750s 147.715us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.910s 122.862us 5 5 100.00
edn_csr_rw 1.010s 17.211us 20 20 100.00
edn_csr_aliasing 1.520s 78.352us 5 5 100.00
edn_same_csr_outstanding 1.750s 147.715us 20 20 100.00
V2 TOTAL 790 790 100.00
V2S tl_intg_err edn_sec_cm 14.040s 999.148us 5 5 100.00
edn_tl_intg_err 2.640s 94.409us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.030s 28.869us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.360s 191.804us 50 50 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 14.040s 999.148us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 14.040s 999.148us 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 14.040s 999.148us 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 14.040s 999.148us 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.360s 191.804us 50 50 100.00
edn_sec_cm 14.040s 999.148us 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.360s 191.804us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 2.640s 94.409us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 34.582m 183.274ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 980 980 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
94.41 98.24 93.74 97.07 84.30 96.62 99.77 91.12

Past Results