EDN Simulation Results

Tuesday June 04 2024 19:02:20 UTC

GitHub Revision: a182fcef27

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 115716131103921631007013649731972014580281041353363476420230431751664670300928

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.050s 20.254us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.950s 30.278us 5 5 100.00
V1 csr_rw edn_csr_rw 0.980s 14.237us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 6.430s 254.274us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.500s 35.202us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.020s 30.708us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.980s 14.237us 20 20 100.00
edn_csr_aliasing 1.500s 35.202us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 5.500s 751.551us 300 300 100.00
V2 csrng_commands edn_genbits 5.500s 751.551us 300 300 100.00
V2 genbits edn_genbits 5.500s 751.551us 300 300 100.00
V2 interrupts edn_intr 1.290s 21.261us 50 50 100.00
V2 alerts edn_alert 1.400s 37.825us 50 50 100.00
V2 errs edn_err 1.370s 27.032us 100 100 100.00
V2 disable edn_disable 1.030s 13.719us 50 50 100.00
edn_disable_auto_req_mode 1.540s 54.423us 50 50 100.00
V2 stress_all edn_stress_all 6.910s 359.152us 50 50 100.00
V2 intr_test edn_intr_test 1.000s 14.793us 50 50 100.00
V2 alert_test edn_alert_test 1.140s 19.992us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.210s 345.852us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.210s 345.852us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.950s 30.278us 5 5 100.00
edn_csr_rw 0.980s 14.237us 20 20 100.00
edn_csr_aliasing 1.500s 35.202us 5 5 100.00
edn_same_csr_outstanding 1.510s 38.281us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.950s 30.278us 5 5 100.00
edn_csr_rw 0.980s 14.237us 20 20 100.00
edn_csr_aliasing 1.500s 35.202us 5 5 100.00
edn_same_csr_outstanding 1.510s 38.281us 20 20 100.00
V2 TOTAL 790 790 100.00
V2S tl_intg_err edn_sec_cm 7.970s 1.975ms 5 5 100.00
edn_tl_intg_err 2.630s 644.129us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.000s 16.056us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.400s 37.825us 50 50 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 7.970s 1.975ms 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 7.970s 1.975ms 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 7.970s 1.975ms 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 7.970s 1.975ms 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.400s 37.825us 50 50 100.00
edn_sec_cm 7.970s 1.975ms 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.400s 37.825us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 2.630s 644.129us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 42.645m 1.296s 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 980 980 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
94.53 98.24 93.80 97.07 84.88 96.62 99.77 91.31

Past Results