EDN Simulation Results

Wednesday June 05 2024 22:14:46 UTC

GitHub Revision: b29ffbb03c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 104714960319679935410420483500971829136303708457300037460974663680452494898918

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.050s	18.711us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.950s	56.015us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.960s	15.548us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	3.480s	91.869us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.220s	27.435us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	2.170s	112.696us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.960s	15.548us	20	20	100.00
		edn_csr_aliasing	1.220s	27.435us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	2.030m	8.759ms	300	300	100.00
V2	csrng_commands	edn_genbits	2.030m	8.759ms	300	300	100.00
V2	genbits	edn_genbits	2.030m	8.759ms	300	300	100.00
V2	interrupts	edn_intr	1.220s	22.011us	50	50	100.00
V2	alerts	edn_alert	1.390s	288.165us	50	50	100.00
V2	errs	edn_err	1.350s	48.736us	100	100	100.00
V2	disable	edn_disable	1.000s	14.123us	50	50	100.00
		edn_disable_auto_req_mode	1.260s	51.602us	50	50	100.00
V2	stress_all	edn_stress_all	6.970s	345.471us	50	50	100.00
V2	intr_test	edn_intr_test	1.000s	15.308us	50	50	100.00
V2	alert_test	edn_alert_test	1.110s	24.899us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	3.660s	238.009us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	3.660s	238.009us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.950s	56.015us	5	5	100.00
		edn_csr_rw	0.960s	15.548us	20	20	100.00
		edn_csr_aliasing	1.220s	27.435us	5	5	100.00
		edn_same_csr_outstanding	1.490s	40.562us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.950s	56.015us	5	5	100.00
		edn_csr_rw	0.960s	15.548us	20	20	100.00
		edn_csr_aliasing	1.220s	27.435us	5	5	100.00
		edn_same_csr_outstanding	1.490s	40.562us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	tl_intg_err	edn_sec_cm	7.920s	1.046ms	5	5	100.00
		edn_tl_intg_err	3.550s	337.648us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.110s	19.269us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.390s	288.165us	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	7.920s	1.046ms	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	7.920s	1.046ms	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	7.920s	1.046ms	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	7.920s	1.046ms	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.390s	288.165us	50	50	100.00
		edn_sec_cm	7.920s	1.046ms	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.390s	288.165us	50	50	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	3.550s	337.648us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	47.520m	123.389ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			980	980	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.27	98.24	93.80	97.02	83.14	96.62	99.77	91.31

Past Results

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• 2024.06.05_03.40.23
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• 2024.05.29_03.03.43
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