EDN Simulation Results

Thursday June 06 2024 19:04:47 UTC

GitHub Revision: `32d52b8d41`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 59908589074363629542901507660786833114562191729708937078847065421241135561861

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.060s	20.964us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.990s	17.844us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.990s	53.494us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	6.230s	519.921us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.530s	70.313us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.970s	52.410us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.990s	53.494us	20	20	100.00
		edn_csr_aliasing	1.530s	70.313us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	1.462m	4.584ms	300	300	100.00
V2	csrng_commands	edn_genbits	1.462m	4.584ms	300	300	100.00
V2	genbits	edn_genbits	1.462m	4.584ms	300	300	100.00
V2	interrupts	edn_intr	1.270s	21.596us	50	50	100.00
V2	alerts	edn_alert	1.350s	29.543us	43	50	86.00
V2	errs	edn_err	1.530s	33.320us	100	100	100.00
V2	disable	edn_disable	7.890s	500.000us	49	50	98.00
		edn_disable_auto_req_mode	1.470s	47.565us	50	50	100.00
V2	stress_all	edn_stress_all	7.950s	423.577us	50	50	100.00
V2	intr_test	edn_intr_test	0.980s	25.407us	50	50	100.00
V2	alert_test	edn_alert_test	1.950s	153.327us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.310s	281.029us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.310s	281.029us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.990s	17.844us	5	5	100.00
		edn_csr_rw	0.990s	53.494us	20	20	100.00
		edn_csr_aliasing	1.530s	70.313us	5	5	100.00
		edn_same_csr_outstanding	1.490s	40.039us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.990s	17.844us	5	5	100.00
		edn_csr_rw	0.990s	53.494us	20	20	100.00
		edn_csr_aliasing	1.530s	70.313us	5	5	100.00
		edn_same_csr_outstanding	1.490s	40.039us	20	20	100.00
V2		TOTAL			782	790	98.99
V2S	tl_intg_err	edn_sec_cm	9.010s	1.988ms	5	5	100.00
		edn_tl_intg_err	3.860s	181.793us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.990s	33.379us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.350s	29.543us	43	50	86.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	9.010s	1.988ms	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	9.010s	1.988ms	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	9.010s	1.988ms	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	9.010s	1.988ms	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.350s	29.543us	43	50	86.00
		edn_sec_cm	9.010s	1.988ms	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.350s	29.543us	43	50	86.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	3.860s	181.793us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	42.135m	109.310ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			972	980	99.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	9	81.82
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.49	98.24	93.72	97.02	92.44	96.33	99.77	90.93

Failure Buckets

Offending 'valid' has 7 failures:

Test edn_alert has 7 failures.

7.edn_alert.7885573784322665792229990912511849158222104944630391818093175523053570979242
Line 280, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/7.edn_alert/latest/run.log

      Offending 'valid'
  UVM_ERROR @   6388208 ps: (push_pull_if.sv:124) [ASSERT FAILED] ValidHighUntilReady_A
  UVM_INFO @   6388208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.edn_alert.95278220915232306217174486167838730863190092399476915941908330981875636213287
Line 280, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/9.edn_alert/latest/run.log

      Offending 'valid'
  UVM_ERROR @  16339848 ps: (push_pull_if.sv:124) [ASSERT FAILED] ValidHighUntilReady_A
  UVM_INFO @  16339848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test edn_disable has 1 failures.
  - 20.edn_disable.17882167319727766655685620548779690763283603421932406460892072878924958806090
    Line 258, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/20.edn_disable/latest/run.log
```
  UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```