EDN Simulation Results

Saturday June 08 2024 00:41:57 UTC

GitHub Revision: `302b24f3c6`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 32491226968592963393132943636196950930602503490106290691157604759716956925599

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.070s	18.345us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.980s	14.334us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.980s	15.842us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	6.920s	1.307ms	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.710s	57.977us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.860s	463.846us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.980s	15.842us	20	20	100.00
		edn_csr_aliasing	1.710s	57.977us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	2.012m	9.130ms	300	300	100.00
V2	csrng_commands	edn_genbits	2.012m	9.130ms	300	300	100.00
V2	genbits	edn_genbits	2.012m	9.130ms	300	300	100.00
V2	interrupts	edn_intr	1.130s	21.448us	50	50	100.00
V2	alerts	edn_alert	1.340s	31.927us	47	50	94.00
V2	errs	edn_err	1.600s	36.700us	100	100	100.00
V2	disable	edn_disable	0.960s	14.880us	50	50	100.00
		edn_disable_auto_req_mode	1.390s	220.936us	50	50	100.00
V2	stress_all	edn_stress_all	6.600s	339.610us	50	50	100.00
V2	intr_test	edn_intr_test	0.970s	17.937us	50	50	100.00
V2	alert_test	edn_alert_test	1.320s	68.994us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.410s	644.398us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.410s	644.398us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.980s	14.334us	5	5	100.00
		edn_csr_rw	0.980s	15.842us	20	20	100.00
		edn_csr_aliasing	1.710s	57.977us	5	5	100.00
		edn_same_csr_outstanding	1.440s	143.433us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.980s	14.334us	5	5	100.00
		edn_csr_rw	0.980s	15.842us	20	20	100.00
		edn_csr_aliasing	1.710s	57.977us	5	5	100.00
		edn_same_csr_outstanding	1.440s	143.433us	20	20	100.00
V2		TOTAL			787	790	99.62
V2S	tl_intg_err	edn_sec_cm	10.080s	661.785us	5	5	100.00
		edn_tl_intg_err	3.070s	222.570us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.020s	18.018us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.340s	31.927us	47	50	94.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	10.080s	661.785us	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	10.080s	661.785us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	10.080s	661.785us	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	10.080s	661.785us	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.340s	31.927us	47	50	94.00
		edn_sec_cm	10.080s	661.785us	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.340s	31.927us	47	50	94.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	3.070s	222.570us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	46.255m	471.652ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			977	980	99.69

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	10	90.91
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.47	98.24	93.78	97.02	91.86	96.33	99.77	91.31

Failure Buckets

Offending 'valid' has 3 failures:

Test edn_alert has 3 failures.

5.edn_alert.52954848984164028374073607592732917949508751198677525166404041783785349175617
Line 280, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/5.edn_alert/latest/run.log

      Offending 'valid'
  UVM_ERROR @   6320297 ps: (push_pull_if.sv:124) [ASSERT FAILED] ValidHighUntilReady_A
  UVM_INFO @   6320297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.edn_alert.55682591297216907644424080140980388838496886110119193725842227676456120364619
Line 280, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/6.edn_alert/latest/run.log

      Offending 'valid'
  UVM_ERROR @   7336069 ps: (push_pull_if.sv:124) [ASSERT FAILED] ValidHighUntilReady_A
  UVM_INFO @   7336069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.