EDN Simulation Results

Sunday June 09 2024 19:02:32 UTC

GitHub Revision: `f92a5ee77b`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 74888572473032497941251936200792687439223302665780333354656685678472336958420

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.050s	17.933us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.020s	69.741us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.980s	27.328us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	6.910s	1.005ms	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.630s	79.767us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	2.000s	150.198us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.980s	27.328us	20	20	100.00
		edn_csr_aliasing	1.630s	79.767us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	2.258m	10.402ms	300	300	100.00
V2	csrng_commands	edn_genbits	2.258m	10.402ms	300	300	100.00
V2	genbits	edn_genbits	2.258m	10.402ms	300	300	100.00
V2	interrupts	edn_intr	1.290s	20.572us	50	50	100.00
V2	alerts	edn_alert	1.510s	370.484us	44	50	88.00
V2	errs	edn_err	1.570s	35.514us	100	100	100.00
V2	disable	edn_disable	1.010s	19.810us	50	50	100.00
		edn_disable_auto_req_mode	1.430s	44.656us	50	50	100.00
V2	stress_all	edn_stress_all	7.260s	389.212us	50	50	100.00
V2	intr_test	edn_intr_test	1.020s	15.535us	50	50	100.00
V2	alert_test	edn_alert_test	1.150s	28.937us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.190s	425.456us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.190s	425.456us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.020s	69.741us	5	5	100.00
		edn_csr_rw	0.980s	27.328us	20	20	100.00
		edn_csr_aliasing	1.630s	79.767us	5	5	100.00
		edn_same_csr_outstanding	1.480s	68.921us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.020s	69.741us	5	5	100.00
		edn_csr_rw	0.980s	27.328us	20	20	100.00
		edn_csr_aliasing	1.630s	79.767us	5	5	100.00
		edn_same_csr_outstanding	1.480s	68.921us	20	20	100.00
V2		TOTAL			784	790	99.24
V2S	tl_intg_err	edn_sec_cm	8.560s	551.409us	5	5	100.00
		edn_tl_intg_err	3.040s	179.204us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.060s	14.720us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.510s	370.484us	44	50	88.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	8.560s	551.409us	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	8.560s	551.409us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	8.560s	551.409us	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	8.560s	551.409us	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.510s	370.484us	44	50	88.00
		edn_sec_cm	8.560s	551.409us	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.510s	370.484us	44	50	88.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	3.040s	179.204us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	36.206m	357.142ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			974	980	99.39

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	10	90.91
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.47	98.24	93.78	97.02	91.86	96.33	99.77	91.31

Failure Buckets

Offending 'valid' has 6 failures:

Test edn_alert has 6 failures.

10.edn_alert.28329599858361510935570175961306956282070826661055084207796601218797440092247
Line 280, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/10.edn_alert/latest/run.log

      Offending 'valid'
  UVM_ERROR @   4824530 ps: (push_pull_if.sv:124) [ASSERT FAILED] ValidHighUntilReady_A
  UVM_INFO @   4824530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

26.edn_alert.74680867399986661745756914211091166336543903329319607820605930990706570500235
Line 280, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/26.edn_alert/latest/run.log

      Offending 'valid'
  UVM_ERROR @  22530400 ps: (push_pull_if.sv:124) [ASSERT FAILED] ValidHighUntilReady_A
  UVM_INFO @  22530400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.