EDN Simulation Results

Monday June 10 2024 23:28:43 UTC

GitHub Revision: `a8c9c17a8c`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 72227341233107832543509484606850665418885932500709631655793413524197290927900

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.160s	17.151us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.030s	22.417us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.980s	107.202us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	5.740s	216.802us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.620s	41.731us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	2.360s	558.500us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.980s	107.202us	20	20	100.00
		edn_csr_aliasing	1.620s	41.731us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	1.394m	4.117ms	300	300	100.00
V2	csrng_commands	edn_genbits	1.394m	4.117ms	300	300	100.00
V2	genbits	edn_genbits	1.394m	4.117ms	300	300	100.00
V2	interrupts	edn_intr	1.230s	20.366us	50	50	100.00
V2	alerts	edn_alert	1.390s	201.140us	49	50	98.00
V2	errs	edn_err	1.420s	29.809us	100	100	100.00
V2	disable	edn_disable	8.110s	500.000us	48	50	96.00
		edn_disable_auto_req_mode	1.520s	51.453us	50	50	100.00
V2	stress_all	edn_stress_all	6.670s	334.849us	50	50	100.00
V2	intr_test	edn_intr_test	1.000s	13.698us	50	50	100.00
V2	alert_test	edn_alert_test	1.280s	151.476us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	3.760s	200.495us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	3.760s	200.495us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.030s	22.417us	5	5	100.00
		edn_csr_rw	0.980s	107.202us	20	20	100.00
		edn_csr_aliasing	1.620s	41.731us	5	5	100.00
		edn_same_csr_outstanding	1.470s	312.593us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.030s	22.417us	5	5	100.00
		edn_csr_rw	0.980s	107.202us	20	20	100.00
		edn_csr_aliasing	1.620s	41.731us	5	5	100.00
		edn_same_csr_outstanding	1.470s	312.593us	20	20	100.00
V2		TOTAL			787	790	99.62
V2S	tl_intg_err	edn_sec_cm	7.890s	993.152us	5	5	100.00
		edn_tl_intg_err	4.050s	220.820us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.080s	19.724us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.390s	201.140us	49	50	98.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	7.890s	993.152us	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	7.890s	993.152us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	7.890s	993.152us	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	7.890s	993.152us	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.390s	201.140us	49	50	98.00
		edn_sec_cm	7.890s	993.152us	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.390s	201.140us	49	50	98.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	4.050s	220.820us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	49.632m	434.101ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			976	980	99.59

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	9	81.82
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.56	98.24	93.78	97.02	91.86	96.33	99.77	91.89

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test edn_disable has 2 failures.
  - 7.edn_disable.77248377878886269752415367857308029381769868199412206862464016627747548065838
    Line 258, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/7.edn_disable/latest/run.log
```
  UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 33.edn_disable.3603937750543549359844064696241440327034617545341996764553469179339733212921
    Line 258, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/33.edn_disable/latest/run.log
```
  UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending 'valid' has 1 failures:
- Test edn_alert has 1 failures.
  - 32.edn_alert.25627049175654478129456413859989586112987722672951971971516383542945511277290
    Line 280, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/32.edn_alert/latest/run.log
```
      Offending 'valid'
  UVM_ERROR @   7668945 ps: (push_pull_if.sv:124) [ASSERT FAILED] ValidHighUntilReady_A
  UVM_INFO @   7668945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:752) [edn_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test edn_stress_all_with_rand_reset has 1 failures.
  - 36.edn_stress_all_with_rand_reset.87570027608007050634911862881953127225704248001700794711103258169025867692599
    Line 307, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/36.edn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 845231078 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 845231078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

EDN Simulation Results

Monday June 10 2024 23:28:43 UTC

GitHub Revision: a8c9c17a8c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 72227341233107832543509484606850665418885932500709631655793413524197290927900

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `a8c9c17a8c`