EDN Simulation Results

Tuesday June 11 2024 19:02:38 UTC

GitHub Revision: dd5ad5fb77

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 66418170746903624595625818392428707033482455256751560525176982524210226376736

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.120s	18.303us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.910s	24.454us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.990s	15.381us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	5.150s	358.142us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.640s	82.244us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	2.190s	32.654us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.990s	15.381us	20	20	100.00
		edn_csr_aliasing	1.640s	82.244us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	1.381m	2.851ms	300	300	100.00
V2	csrng_commands	edn_genbits	1.381m	2.851ms	300	300	100.00
V2	genbits	edn_genbits	1.381m	2.851ms	300	300	100.00
V2	interrupts	edn_intr	1.310s	23.218us	50	50	100.00
V2	alerts	edn_alert	1.460s	379.647us	200	200	100.00
V2	errs	edn_err	1.400s	31.646us	100	100	100.00
V2	disable	edn_disable	8.220s	500.000us	49	50	98.00
		edn_disable_auto_req_mode	1.500s	49.031us	50	50	100.00
V2	stress_all	edn_stress_all	7.700s	378.370us	50	50	100.00
V2	intr_test	edn_intr_test	0.990s	15.306us	50	50	100.00
V2	alert_test	edn_alert_test	1.440s	51.215us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.610s	143.764us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.610s	143.764us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.910s	24.454us	5	5	100.00
		edn_csr_rw	0.990s	15.381us	20	20	100.00
		edn_csr_aliasing	1.640s	82.244us	5	5	100.00
		edn_same_csr_outstanding	1.440s	71.208us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.910s	24.454us	5	5	100.00
		edn_csr_rw	0.990s	15.381us	20	20	100.00
		edn_csr_aliasing	1.640s	82.244us	5	5	100.00
		edn_same_csr_outstanding	1.440s	71.208us	20	20	100.00
V2		TOTAL			939	940	99.89
V2S	tl_intg_err	edn_sec_cm	11.110s	770.121us	5	5	100.00
		edn_tl_intg_err	7.350s	439.269us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.020s	20.334us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.460s	379.647us	200	200	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	11.110s	770.121us	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	11.110s	770.121us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	11.110s	770.121us	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	11.110s	770.121us	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.460s	379.647us	200	200	100.00
		edn_sec_cm	11.110s	770.121us	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.460s	379.647us	200	200	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	7.350s	439.269us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	1.003h	158.022ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1129	1130	99.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	10	90.91
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.76	98.25	93.97	97.02	93.02	96.37	99.77	91.89

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test edn_disable has 1 failures.

    • 47.edn_disable.110731335924853565193438959714332728531546894504133415967249812821660852892786
      Line 258, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/47.edn_disable/latest/run.log

        UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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