EDN Simulation Results

Thursday June 13 2024 19:02:12 UTC

GitHub Revision: 548a3880d8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 95435389850697596633112362018639443702533575559488568730544091582583938649085

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.080s 19.037us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.060s 20.540us 5 5 100.00
V1 csr_rw edn_csr_rw 1.320s 43.787us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 5.140s 347.194us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.520s 276.546us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.050s 113.609us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.320s 43.787us 20 20 100.00
edn_csr_aliasing 1.520s 276.546us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 1.572m 9.101ms 300 300 100.00
V2 csrng_commands edn_genbits 1.572m 9.101ms 300 300 100.00
V2 genbits edn_genbits 1.572m 9.101ms 300 300 100.00
V2 interrupts edn_intr 1.290s 30.186us 50 50 100.00
V2 alerts edn_alert 1.760s 345.862us 200 200 100.00
V2 errs edn_err 1.540s 36.482us 100 100 100.00
V2 disable edn_disable 0.980s 13.898us 50 50 100.00
edn_disable_auto_req_mode 1.500s 51.293us 50 50 100.00
V2 stress_all edn_stress_all 7.460s 382.377us 50 50 100.00
V2 intr_test edn_intr_test 0.980s 17.971us 50 50 100.00
V2 alert_test edn_alert_test 1.160s 58.111us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 3.870s 157.422us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 3.870s 157.422us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.060s 20.540us 5 5 100.00
edn_csr_rw 1.320s 43.787us 20 20 100.00
edn_csr_aliasing 1.520s 276.546us 5 5 100.00
edn_same_csr_outstanding 1.460s 116.179us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.060s 20.540us 5 5 100.00
edn_csr_rw 1.320s 43.787us 20 20 100.00
edn_csr_aliasing 1.520s 276.546us 5 5 100.00
edn_same_csr_outstanding 1.460s 116.179us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 8.880s 3.620ms 5 5 100.00
edn_tl_intg_err 3.320s 224.923us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.030s 20.756us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.760s 345.862us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 8.880s 3.620ms 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 8.880s 3.620ms 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 8.880s 3.620ms 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 8.880s 3.620ms 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.760s 345.862us 200 200 100.00
edn_sec_cm 8.880s 3.620ms 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.760s 345.862us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 3.320s 224.923us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 1.027h 1.135s 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 1130 1130 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.78 98.25 93.91 97.02 93.02 96.37 99.77 92.08

Past Results