EDN Simulation Results

Friday June 21 2024 23:02:45 UTC

GitHub Revision: de38ce313c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 40294666978553523170681160506532247841705182588034413483474981853853670477454

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.080s 20.315us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.010s 16.914us 5 5 100.00
V1 csr_rw edn_csr_rw 1.080s 19.126us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 3.870s 166.188us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.650s 49.512us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.910s 108.409us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.080s 19.126us 20 20 100.00
edn_csr_aliasing 1.650s 49.512us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 1.243m 2.294ms 300 300 100.00
V2 csrng_commands edn_genbits 1.243m 2.294ms 300 300 100.00
V2 genbits edn_genbits 1.243m 2.294ms 300 300 100.00
V2 interrupts edn_intr 1.240s 33.335us 50 50 100.00
V2 alerts edn_alert 1.390s 34.304us 200 200 100.00
V2 errs edn_err 1.340s 29.444us 100 100 100.00
V2 disable edn_disable 1.050s 39.097us 50 50 100.00
edn_disable_auto_req_mode 1.860s 53.783us 50 50 100.00
V2 stress_all edn_stress_all 8.200s 455.801us 50 50 100.00
V2 intr_test edn_intr_test 1.010s 16.333us 50 50 100.00
V2 alert_test edn_alert_test 1.030s 29.684us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.010s 102.957us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.010s 102.957us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.010s 16.914us 5 5 100.00
edn_csr_rw 1.080s 19.126us 20 20 100.00
edn_csr_aliasing 1.650s 49.512us 5 5 100.00
edn_same_csr_outstanding 1.570s 323.218us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.010s 16.914us 5 5 100.00
edn_csr_rw 1.080s 19.126us 20 20 100.00
edn_csr_aliasing 1.650s 49.512us 5 5 100.00
edn_same_csr_outstanding 1.570s 323.218us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 12.640s 852.848us 5 5 100.00
edn_tl_intg_err 8.660s 494.067us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.030s 19.092us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.390s 34.304us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 12.640s 852.848us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 12.640s 852.848us 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 12.640s 852.848us 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 12.640s 852.848us 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.390s 34.304us 200 200 100.00
edn_sec_cm 12.640s 852.848us 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.390s 34.304us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 8.660s 494.067us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 45.419m 228.355ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 1130 1130 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.51 98.25 93.97 97.07 91.28 96.37 99.77 91.89

Past Results