EDN Simulation Results

Saturday June 22 2024 23:02:20 UTC

GitHub Revision: 8fdb25c8d9

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 116774179587740886356693500529232784059703555433764635649168222249757162669

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.080s 17.281us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.930s 14.093us 5 5 100.00
V1 csr_rw edn_csr_rw 0.960s 275.417us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 6.280s 905.633us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.660s 149.097us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.020s 174.468us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.960s 275.417us 20 20 100.00
edn_csr_aliasing 1.660s 149.097us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 1.215m 2.261ms 300 300 100.00
V2 csrng_commands edn_genbits 1.215m 2.261ms 300 300 100.00
V2 genbits edn_genbits 1.215m 2.261ms 300 300 100.00
V2 interrupts edn_intr 1.260s 22.078us 50 50 100.00
V2 alerts edn_alert 1.590s 228.052us 200 200 100.00
V2 errs edn_err 1.390s 28.763us 100 100 100.00
V2 disable edn_disable 1.050s 12.079us 50 50 100.00
edn_disable_auto_req_mode 1.650s 54.018us 50 50 100.00
V2 stress_all edn_stress_all 7.890s 431.210us 50 50 100.00
V2 intr_test edn_intr_test 0.990s 18.539us 50 50 100.00
V2 alert_test edn_alert_test 1.610s 59.904us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.720s 141.405us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.720s 141.405us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.930s 14.093us 5 5 100.00
edn_csr_rw 0.960s 275.417us 20 20 100.00
edn_csr_aliasing 1.660s 149.097us 5 5 100.00
edn_same_csr_outstanding 1.580s 260.006us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.930s 14.093us 5 5 100.00
edn_csr_rw 0.960s 275.417us 20 20 100.00
edn_csr_aliasing 1.660s 149.097us 5 5 100.00
edn_same_csr_outstanding 1.580s 260.006us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 8.630s 615.049us 5 5 100.00
edn_tl_intg_err 3.060s 604.842us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.040s 17.005us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.590s 228.052us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 8.630s 615.049us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 8.630s 615.049us 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 8.630s 615.049us 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 8.630s 615.049us 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.590s 228.052us 200 200 100.00
edn_sec_cm 8.630s 615.049us 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.590s 228.052us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 3.060s 604.842us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 45.084m 184.926ms 49 50 98.00
V3 TOTAL 49 50 98.00
TOTAL 1129 1130 99.91

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.62 98.25 93.97 97.02 91.86 96.37 99.77 92.08

Failure Buckets

Past Results