EDN Simulation Results

Sunday June 23 2024 23:02:35 UTC

GitHub Revision: 25e609d6bb

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 43520053114197278442322840927374150239284669988213580416404649115121474470865

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.090s 18.359us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.990s 19.779us 5 5 100.00
V1 csr_rw edn_csr_rw 1.000s 17.455us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 4.900s 348.684us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.470s 239.142us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.820s 178.734us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.000s 17.455us 20 20 100.00
edn_csr_aliasing 1.470s 239.142us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 8.340s 1.048ms 300 300 100.00
V2 csrng_commands edn_genbits 8.340s 1.048ms 300 300 100.00
V2 genbits edn_genbits 8.340s 1.048ms 300 300 100.00
V2 interrupts edn_intr 1.240s 21.500us 50 50 100.00
V2 alerts edn_alert 1.480s 34.823us 200 200 100.00
V2 errs edn_err 1.270s 25.500us 100 100 100.00
V2 disable edn_disable 0.980s 33.584us 50 50 100.00
edn_disable_auto_req_mode 1.510s 45.183us 50 50 100.00
V2 stress_all edn_stress_all 6.900s 367.895us 50 50 100.00
V2 intr_test edn_intr_test 0.990s 18.663us 50 50 100.00
V2 alert_test edn_alert_test 1.150s 29.787us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.710s 940.964us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.710s 940.964us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.990s 19.779us 5 5 100.00
edn_csr_rw 1.000s 17.455us 20 20 100.00
edn_csr_aliasing 1.470s 239.142us 5 5 100.00
edn_same_csr_outstanding 1.810s 643.441us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.990s 19.779us 5 5 100.00
edn_csr_rw 1.000s 17.455us 20 20 100.00
edn_csr_aliasing 1.470s 239.142us 5 5 100.00
edn_same_csr_outstanding 1.810s 643.441us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 9.210s 604.792us 5 5 100.00
edn_tl_intg_err 4.460s 211.917us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.040s 19.462us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.480s 34.823us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 9.210s 604.792us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 9.210s 604.792us 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 9.210s 604.792us 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 9.210s 604.792us 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.480s 34.823us 200 200 100.00
edn_sec_cm 9.210s 604.792us 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.480s 34.823us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 4.460s 211.917us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 49.211m 826.459ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 1130 1130 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.53 98.25 93.91 97.02 91.28 96.37 99.77 92.08

Past Results