EDN Simulation Results

Monday June 24 2024 23:02:35 UTC

GitHub Revision: 6e698b4dfe

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 102849012855470111388983783327793201144267754054590670930996118558901483180117

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.080s	18.350us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.040s	15.976us	5	5	100.00
V1	csr_rw	edn_csr_rw	1.010s	19.854us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	5.100s	182.377us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.560s	71.312us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.740s	53.470us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.010s	19.854us	20	20	100.00
		edn_csr_aliasing	1.560s	71.312us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	2.071m	9.131ms	300	300	100.00
V2	csrng_commands	edn_genbits	2.071m	9.131ms	300	300	100.00
V2	genbits	edn_genbits	2.071m	9.131ms	300	300	100.00
V2	interrupts	edn_intr	1.290s	23.214us	50	50	100.00
V2	alerts	edn_alert	1.490s	422.001us	200	200	100.00
V2	errs	edn_err	1.390s	38.837us	100	100	100.00
V2	disable	edn_disable	0.960s	24.140us	50	50	100.00
		edn_disable_auto_req_mode	1.610s	60.696us	49	50	98.00
V2	stress_all	edn_stress_all	7.230s	363.237us	50	50	100.00
V2	intr_test	edn_intr_test	0.980s	17.847us	50	50	100.00
V2	alert_test	edn_alert_test	1.130s	27.763us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.570s	606.037us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.570s	606.037us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.040s	15.976us	5	5	100.00
		edn_csr_rw	1.010s	19.854us	20	20	100.00
		edn_csr_aliasing	1.560s	71.312us	5	5	100.00
		edn_same_csr_outstanding	1.490s	70.122us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.040s	15.976us	5	5	100.00
		edn_csr_rw	1.010s	19.854us	20	20	100.00
		edn_csr_aliasing	1.560s	71.312us	5	5	100.00
		edn_same_csr_outstanding	1.490s	70.122us	20	20	100.00
V2		TOTAL			939	940	99.89
V2S	tl_intg_err	edn_sec_cm	10.000s	660.460us	5	5	100.00
		edn_tl_intg_err	3.930s	375.505us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.070s	19.128us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.490s	422.001us	200	200	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	10.000s	660.460us	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	10.000s	660.460us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	10.000s	660.460us	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	10.000s	660.460us	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.490s	422.001us	200	200	100.00
		edn_sec_cm	10.000s	660.460us	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.490s	422.001us	200	200	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	3.930s	375.505us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	1.064h	535.040ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1129	1130	99.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	10	90.91
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.62	98.25	93.91	97.07	91.86	96.37	99.77	92.08

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test edn_disable_auto_req_mode has 1 failures.

    • 14.edn_disable_auto_req_mode.36536089891942851282400296631409838736910607014207971401903800434423870446886
      Line 263, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/14.edn_disable_auto_req_mode/latest/run.log

        UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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