EDN Simulation Results

Tuesday June 25 2024 23:02:40 UTC

GitHub Revision: `3fd3528c8c`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 44317642457786780768002458033256869318159334982704173107202396839344093642292

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.140s	27.540us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.010s	88.635us	5	5	100.00
V1	csr_rw	edn_csr_rw	1.110s	25.691us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	6.330s	266.564us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.230s	17.713us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.820s	50.389us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.110s	25.691us	20	20	100.00
		edn_csr_aliasing	1.230s	17.713us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	1.847m	8.812ms	300	300	100.00
V2	csrng_commands	edn_genbits	1.847m	8.812ms	300	300	100.00
V2	genbits	edn_genbits	1.847m	8.812ms	300	300	100.00
V2	interrupts	edn_intr	1.260s	22.447us	50	50	100.00
V2	alerts	edn_alert	1.730s	474.612us	200	200	100.00
V2	errs	edn_err	1.440s	38.796us	100	100	100.00
V2	disable	edn_disable	1.000s	14.271us	50	50	100.00
		edn_disable_auto_req_mode	1.410s	81.739us	49	50	98.00
V2	stress_all	edn_stress_all	7.200s	593.364us	50	50	100.00
V2	intr_test	edn_intr_test	1.030s	17.633us	50	50	100.00
V2	alert_test	edn_alert_test	1.430s	48.038us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.110s	123.431us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.110s	123.431us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.010s	88.635us	5	5	100.00
		edn_csr_rw	1.110s	25.691us	20	20	100.00
		edn_csr_aliasing	1.230s	17.713us	5	5	100.00
		edn_same_csr_outstanding	1.510s	134.493us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.010s	88.635us	5	5	100.00
		edn_csr_rw	1.110s	25.691us	20	20	100.00
		edn_csr_aliasing	1.230s	17.713us	5	5	100.00
		edn_same_csr_outstanding	1.510s	134.493us	20	20	100.00
V2		TOTAL			939	940	99.89
V2S	tl_intg_err	edn_sec_cm	4.980s	270.534us	5	5	100.00
		edn_tl_intg_err	4.910s	1.022ms	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.040s	18.063us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.730s	474.612us	200	200	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	4.980s	270.534us	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	4.980s	270.534us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	4.980s	270.534us	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	4.980s	270.534us	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.730s	474.612us	200	200	100.00
		edn_sec_cm	4.980s	270.534us	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.730s	474.612us	200	200	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	4.910s	1.022ms	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	42.147m	106.460ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1128	1130	99.82

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	10	90.91
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.60	98.25	93.67	97.02	91.86	96.37	99.77	92.28

Failure Buckets

UVM_FATAL (edn_scoreboard.sv:578) [scoreboard] Check failed (reqs_between_reseeds_ctr < max_num_reqs_between_reseeds) Maximum number of request between reseeds in auto_req_mode * exceeded. has 1 failures:
- Test edn_disable_auto_req_mode has 1 failures.
  - 5.edn_disable_auto_req_mode.9490487078352486892907227434142308217202209888580118450560084619389582967688
    Line 263, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/5.edn_disable_auto_req_mode/latest/run.log
```
  UVM_FATAL @  35411845 ps: (edn_scoreboard.sv:578) [uvm_test_top.env.scoreboard] Check failed (reqs_between_reseeds_ctr < max_num_reqs_between_reseeds) Maximum number of request between reseeds in auto_req_mode 0x00000001 exceeded.
  UVM_INFO @  35411845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:752) [edn_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test edn_stress_all_with_rand_reset has 1 failures.
  - 11.edn_stress_all_with_rand_reset.24203332431988555178647671985135620219863543270256423641236675168046710310909
    Line 711, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/11.edn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 26659227731 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 26659227731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

EDN Simulation Results

Tuesday June 25 2024 23:02:40 UTC

GitHub Revision: 3fd3528c8c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 44317642457786780768002458033256869318159334982704173107202396839344093642292

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `3fd3528c8c`