EDN Simulation Results

Wednesday June 26 2024 23:02:36 UTC

GitHub Revision: be1c4a4f52

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 44766564427213563291105655232733134394512207819884794315335669279596867428010

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.070s 17.593us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.980s 19.496us 5 5 100.00
V1 csr_rw edn_csr_rw 0.970s 15.784us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 6.190s 985.775us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.540s 34.834us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.560s 60.663us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.970s 15.784us 20 20 100.00
edn_csr_aliasing 1.540s 34.834us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 5.410s 776.424us 300 300 100.00
V2 csrng_commands edn_genbits 5.410s 776.424us 300 300 100.00
V2 genbits edn_genbits 5.410s 776.424us 300 300 100.00
V2 interrupts edn_intr 1.280s 22.195us 50 50 100.00
V2 alerts edn_alert 1.470s 42.522us 200 200 100.00
V2 errs edn_err 1.540s 34.932us 100 100 100.00
V2 disable edn_disable 0.990s 13.863us 50 50 100.00
edn_disable_auto_req_mode 1.620s 50.570us 50 50 100.00
V2 stress_all edn_stress_all 7.360s 422.424us 50 50 100.00
V2 intr_test edn_intr_test 0.960s 17.516us 50 50 100.00
V2 alert_test edn_alert_test 1.060s 22.106us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.100s 130.237us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.100s 130.237us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.980s 19.496us 5 5 100.00
edn_csr_rw 0.970s 15.784us 20 20 100.00
edn_csr_aliasing 1.540s 34.834us 5 5 100.00
edn_same_csr_outstanding 1.490s 74.567us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.980s 19.496us 5 5 100.00
edn_csr_rw 0.970s 15.784us 20 20 100.00
edn_csr_aliasing 1.540s 34.834us 5 5 100.00
edn_same_csr_outstanding 1.490s 74.567us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 8.280s 918.048us 5 5 100.00
edn_tl_intg_err 9.600s 631.580us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.050s 16.049us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.470s 42.522us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 8.280s 918.048us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 8.280s 918.048us 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 8.280s 918.048us 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 8.280s 918.048us 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.470s 42.522us 200 200 100.00
edn_sec_cm 8.280s 918.048us 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.470s 42.522us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 9.600s 631.580us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 44.309m 212.760ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 1130 1130 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.71 98.25 93.85 97.02 93.02 96.37 99.77 91.70

Past Results