EDN Simulation Results

Thursday June 27 2024 23:02:31 UTC

GitHub Revision: 8db2a18db1

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 100513533386727882033709335126269317053614297947080434367729937568368619502352

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.080s	15.732us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.970s	55.206us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.940s	50.540us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	5.400s	2.841ms	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.590s	69.365us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.830s	49.635us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.940s	50.540us	20	20	100.00
		edn_csr_aliasing	1.590s	69.365us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	2.123m	9.182ms	300	300	100.00
V2	csrng_commands	edn_genbits	2.123m	9.182ms	300	300	100.00
V2	genbits	edn_genbits	2.123m	9.182ms	300	300	100.00
V2	interrupts	edn_intr	1.270s	20.842us	50	50	100.00
V2	alerts	edn_alert	1.560s	406.873us	200	200	100.00
V2	errs	edn_err	1.460s	34.757us	100	100	100.00
V2	disable	edn_disable	3.470s	500.000us	49	50	98.00
		edn_disable_auto_req_mode	1.510s	50.924us	50	50	100.00
V2	stress_all	edn_stress_all	7.360s	380.354us	50	50	100.00
V2	intr_test	edn_intr_test	0.980s	16.386us	50	50	100.00
V2	alert_test	edn_alert_test	1.190s	32.772us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.120s	119.390us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.120s	119.390us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.970s	55.206us	5	5	100.00
		edn_csr_rw	0.940s	50.540us	20	20	100.00
		edn_csr_aliasing	1.590s	69.365us	5	5	100.00
		edn_same_csr_outstanding	1.400s	111.547us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.970s	55.206us	5	5	100.00
		edn_csr_rw	0.940s	50.540us	20	20	100.00
		edn_csr_aliasing	1.590s	69.365us	5	5	100.00
		edn_same_csr_outstanding	1.400s	111.547us	20	20	100.00
V2		TOTAL			939	940	99.89
V2S	tl_intg_err	edn_sec_cm	8.960s	3.341ms	5	5	100.00
		edn_tl_intg_err	3.390s	154.203us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.010s	18.426us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.560s	406.873us	200	200	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	8.960s	3.341ms	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	8.960s	3.341ms	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	8.960s	3.341ms	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	8.960s	3.341ms	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.560s	406.873us	200	200	100.00
		edn_sec_cm	8.960s	3.341ms	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.560s	406.873us	200	200	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	3.390s	154.203us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	40.201m	190.584ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1129	1130	99.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	10	90.91
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.73	98.25	93.97	97.02	92.44	96.37	99.77	92.28

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test edn_disable has 1 failures.

    • 28.edn_disable.101674690204723232812037172657241850825428384979374081459162847493842769572473
      Line 258, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/28.edn_disable/latest/run.log

        UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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