EDN Simulation Results

Friday June 28 2024 23:02:02 UTC

GitHub Revision: 3d5220a43f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 73442097946972310753089853920865571566707682704390544987111276126114608747389

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.110s 16.814us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.980s 23.437us 5 5 100.00
V1 csr_rw edn_csr_rw 1.090s 23.598us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 6.580s 509.664us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.560s 43.899us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.660s 35.996us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.090s 23.598us 20 20 100.00
edn_csr_aliasing 1.560s 43.899us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 2.821m 14.505ms 300 300 100.00
V2 csrng_commands edn_genbits 2.821m 14.505ms 300 300 100.00
V2 genbits edn_genbits 2.821m 14.505ms 300 300 100.00
V2 interrupts edn_intr 1.290s 22.434us 50 50 100.00
V2 alerts edn_alert 1.450s 222.260us 200 200 100.00
V2 errs edn_err 1.350s 57.492us 100 100 100.00
V2 disable edn_disable 1.030s 20.610us 50 50 100.00
edn_disable_auto_req_mode 1.560s 60.115us 50 50 100.00
V2 stress_all edn_stress_all 8.010s 443.178us 50 50 100.00
V2 intr_test edn_intr_test 0.960s 16.640us 50 50 100.00
V2 alert_test edn_alert_test 1.410s 52.519us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.260s 230.715us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.260s 230.715us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.980s 23.437us 5 5 100.00
edn_csr_rw 1.090s 23.598us 20 20 100.00
edn_csr_aliasing 1.560s 43.899us 5 5 100.00
edn_same_csr_outstanding 1.500s 160.984us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.980s 23.437us 5 5 100.00
edn_csr_rw 1.090s 23.598us 20 20 100.00
edn_csr_aliasing 1.560s 43.899us 5 5 100.00
edn_same_csr_outstanding 1.500s 160.984us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 8.300s 507.142us 5 5 100.00
edn_tl_intg_err 4.500s 234.004us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.100s 18.274us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.450s 222.260us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 8.300s 507.142us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 8.300s 507.142us 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 8.300s 507.142us 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 8.300s 507.142us 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.450s 222.260us 200 200 100.00
edn_sec_cm 8.300s 507.142us 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.450s 222.260us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 4.500s 234.004us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 43.891m 245.803ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 1130 1130 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.53 98.25 93.97 97.02 91.28 96.37 99.77 92.08

Past Results