EDN Simulation Results

Saturday June 29 2024 23:02:35 UTC

GitHub Revision: b33f0bcb4a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 9407974028806500767465982655187958599819354731549473124644158596869486113221

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.170s	15.166us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.070s	21.536us	5	5	100.00
V1	csr_rw	edn_csr_rw	1.040s	16.298us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	6.580s	513.207us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.720s	38.898us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	2.210s	57.394us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.040s	16.298us	20	20	100.00
		edn_csr_aliasing	1.720s	38.898us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	5.840s	769.107us	300	300	100.00
V2	csrng_commands	edn_genbits	5.840s	769.107us	300	300	100.00
V2	genbits	edn_genbits	5.840s	769.107us	300	300	100.00
V2	interrupts	edn_intr	1.200s	23.384us	50	50	100.00
V2	alerts	edn_alert	1.480s	271.025us	200	200	100.00
V2	errs	edn_err	1.430s	31.078us	100	100	100.00
V2	disable	edn_disable	0.960s	14.027us	50	50	100.00
		edn_disable_auto_req_mode	1.490s	49.015us	50	50	100.00
V2	stress_all	edn_stress_all	7.560s	377.566us	50	50	100.00
V2	intr_test	edn_intr_test	1.010s	21.274us	50	50	100.00
V2	alert_test	edn_alert_test	1.250s	39.403us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.300s	338.901us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.300s	338.901us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.070s	21.536us	5	5	100.00
		edn_csr_rw	1.040s	16.298us	20	20	100.00
		edn_csr_aliasing	1.720s	38.898us	5	5	100.00
		edn_same_csr_outstanding	1.590s	43.743us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.070s	21.536us	5	5	100.00
		edn_csr_rw	1.040s	16.298us	20	20	100.00
		edn_csr_aliasing	1.720s	38.898us	5	5	100.00
		edn_same_csr_outstanding	1.590s	43.743us	20	20	100.00
V2		TOTAL			940	940	100.00
V2S	tl_intg_err	edn_sec_cm	7.440s	1.750ms	5	5	100.00
		edn_tl_intg_err	2.880s	305.269us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.050s	16.053us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.480s	271.025us	200	200	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	7.440s	1.750ms	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	7.440s	1.750ms	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	7.440s	1.750ms	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	7.440s	1.750ms	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.480s	271.025us	200	200	100.00
		edn_sec_cm	7.440s	1.750ms	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.480s	271.025us	200	200	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.880s	305.269us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	58.568m	1.834s	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1130	1130	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.65	98.25	93.97	97.07	91.86	96.37	99.77	92.28

Past Results

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• lint
• 2024.06.29_09.29.32
• 2024.06.28_11.46.38
• 2024.06.27_11.03.52
• 2024.06.26_11.00.25
• 2024.06.25_11.23.40
• 2024.06.24_08.19.42