EDN Simulation Results

Sunday June 30 2024 23:02:20 UTC

GitHub Revision: b33f0bcb4a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 105302396297609026156504164956156290718642058150905320202190590799028860124396

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.060s 16.521us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.990s 57.336us 5 5 100.00
V1 csr_rw edn_csr_rw 0.990s 17.768us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 6.840s 1.375ms 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.430s 61.017us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.190s 114.152us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.990s 17.768us 20 20 100.00
edn_csr_aliasing 1.430s 61.017us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 1.547m 8.767ms 300 300 100.00
V2 csrng_commands edn_genbits 1.547m 8.767ms 300 300 100.00
V2 genbits edn_genbits 1.547m 8.767ms 300 300 100.00
V2 interrupts edn_intr 1.280s 20.641us 50 50 100.00
V2 alerts edn_alert 1.420s 268.288us 200 200 100.00
V2 errs edn_err 1.450s 29.400us 100 100 100.00
V2 disable edn_disable 0.950s 14.631us 50 50 100.00
edn_disable_auto_req_mode 1.810s 45.717us 50 50 100.00
V2 stress_all edn_stress_all 6.240s 299.300us 50 50 100.00
V2 intr_test edn_intr_test 0.970s 240.055us 50 50 100.00
V2 alert_test edn_alert_test 1.290s 41.497us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 5.390s 589.068us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 5.390s 589.068us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.990s 57.336us 5 5 100.00
edn_csr_rw 0.990s 17.768us 20 20 100.00
edn_csr_aliasing 1.430s 61.017us 5 5 100.00
edn_same_csr_outstanding 1.640s 41.690us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.990s 57.336us 5 5 100.00
edn_csr_rw 0.990s 17.768us 20 20 100.00
edn_csr_aliasing 1.430s 61.017us 5 5 100.00
edn_same_csr_outstanding 1.640s 41.690us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 8.300s 2.205ms 5 5 100.00
edn_tl_intg_err 2.950s 241.176us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.040s 16.644us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.420s 268.288us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 8.300s 2.205ms 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 8.300s 2.205ms 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 8.300s 2.205ms 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 8.300s 2.205ms 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.420s 268.288us 200 200 100.00
edn_sec_cm 8.300s 2.205ms 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.420s 268.288us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 2.950s 241.176us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 41.864m 278.501ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 1130 1130 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.45 98.25 93.91 97.07 90.70 96.37 99.77 92.08

Past Results