EDN Simulation Results

Monday July 01 2024 17:07:21 UTC

GitHub Revision: eb56ef55d0

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 287373712151371957859909226915296476629077008125381265920192201371239303276

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.050s 20.590us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.020s 21.143us 5 5 100.00
V1 csr_rw edn_csr_rw 1.000s 16.190us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 8.320s 4.160ms 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.610s 75.189us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.090s 112.904us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.000s 16.190us 20 20 100.00
edn_csr_aliasing 1.610s 75.189us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 6.950s 867.090us 300 300 100.00
V2 csrng_commands edn_genbits 6.950s 867.090us 300 300 100.00
V2 genbits edn_genbits 6.950s 867.090us 300 300 100.00
V2 interrupts edn_intr 1.210s 22.985us 50 50 100.00
V2 alerts edn_alert 1.570s 432.726us 200 200 100.00
V2 errs edn_err 1.420s 33.579us 100 100 100.00
V2 disable edn_disable 0.940s 13.481us 50 50 100.00
edn_disable_auto_req_mode 1.530s 35.272us 50 50 100.00
V2 stress_all edn_stress_all 6.930s 360.564us 50 50 100.00
V2 intr_test edn_intr_test 0.980s 17.156us 50 50 100.00
V2 alert_test edn_alert_test 1.120s 58.248us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.440s 124.995us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.440s 124.995us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.020s 21.143us 5 5 100.00
edn_csr_rw 1.000s 16.190us 20 20 100.00
edn_csr_aliasing 1.610s 75.189us 5 5 100.00
edn_same_csr_outstanding 1.480s 34.812us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.020s 21.143us 5 5 100.00
edn_csr_rw 1.000s 16.190us 20 20 100.00
edn_csr_aliasing 1.610s 75.189us 5 5 100.00
edn_same_csr_outstanding 1.480s 34.812us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 7.780s 953.021us 5 5 100.00
edn_tl_intg_err 3.050s 138.252us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.020s 17.832us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.570s 432.726us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 7.780s 953.021us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 7.780s 953.021us 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 7.780s 953.021us 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 7.780s 953.021us 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.570s 432.726us 200 200 100.00
edn_sec_cm 7.780s 953.021us 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.570s 432.726us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 3.050s 138.252us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 42.768m 424.878ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 1130 1130 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.66 98.25 93.91 97.02 92.44 96.37 99.77 91.89

Past Results