EDN Simulation Results

Monday July 01 2024 23:02:26 UTC

GitHub Revision: e9ae10fb42

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 81071883735317974084005537723499931298658500385730214730015283368929474034200

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.060s 19.309us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.950s 17.474us 5 5 100.00
V1 csr_rw edn_csr_rw 1.000s 18.088us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 7.190s 1.058ms 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.730s 41.105us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.820s 113.062us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.000s 18.088us 20 20 100.00
edn_csr_aliasing 1.730s 41.105us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 1.462m 4.553ms 300 300 100.00
V2 csrng_commands edn_genbits 1.462m 4.553ms 300 300 100.00
V2 genbits edn_genbits 1.462m 4.553ms 300 300 100.00
V2 interrupts edn_intr 1.440s 54.241us 50 50 100.00
V2 alerts edn_alert 1.480s 31.960us 200 200 100.00
V2 errs edn_err 1.470s 33.352us 100 100 100.00
V2 disable edn_disable 0.990s 14.642us 50 50 100.00
edn_disable_auto_req_mode 1.570s 47.127us 50 50 100.00
V2 stress_all edn_stress_all 7.990s 423.157us 50 50 100.00
V2 intr_test edn_intr_test 1.060s 22.784us 50 50 100.00
V2 alert_test edn_alert_test 1.140s 79.934us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.760s 155.086us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.760s 155.086us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.950s 17.474us 5 5 100.00
edn_csr_rw 1.000s 18.088us 20 20 100.00
edn_csr_aliasing 1.730s 41.105us 5 5 100.00
edn_same_csr_outstanding 1.440s 139.006us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.950s 17.474us 5 5 100.00
edn_csr_rw 1.000s 18.088us 20 20 100.00
edn_csr_aliasing 1.730s 41.105us 5 5 100.00
edn_same_csr_outstanding 1.440s 139.006us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 8.530s 560.039us 5 5 100.00
edn_tl_intg_err 3.360s 165.647us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.000s 18.670us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.480s 31.960us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 8.530s 560.039us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 8.530s 560.039us 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 8.530s 560.039us 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 8.530s 560.039us 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.480s 31.960us 200 200 100.00
edn_sec_cm 8.530s 560.039us 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.480s 31.960us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 3.360s 165.647us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 48.926m 111.752ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 1130 1130 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.83 98.25 93.91 97.02 93.60 96.37 99.77 91.89

Past Results