EDN Simulation Results

Tuesday July 02 2024 14:17:13 UTC

GitHub Revision: abd7ce57f2

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 7120396591488306882161367642496372905152431708445539866860566607772054886363

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.110s 18.631us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.000s 27.828us 5 5 100.00
V1 csr_rw edn_csr_rw 0.980s 15.124us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 6.630s 254.308us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.610s 67.437us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.050s 122.138us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.980s 15.124us 20 20 100.00
edn_csr_aliasing 1.610s 67.437us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 1.101m 2.557ms 300 300 100.00
V2 csrng_commands edn_genbits 1.101m 2.557ms 300 300 100.00
V2 genbits edn_genbits 1.101m 2.557ms 300 300 100.00
V2 interrupts edn_intr 1.230s 22.859us 50 50 100.00
V2 alerts edn_alert 1.700s 362.134us 200 200 100.00
V2 errs edn_err 1.380s 30.095us 100 100 100.00
V2 disable edn_disable 0.980s 12.749us 50 50 100.00
edn_disable_auto_req_mode 1.650s 126.515us 50 50 100.00
V2 stress_all edn_stress_all 6.970s 441.231us 50 50 100.00
V2 intr_test edn_intr_test 1.000s 23.095us 50 50 100.00
V2 alert_test edn_alert_test 1.160s 37.549us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.840s 309.236us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.840s 309.236us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.000s 27.828us 5 5 100.00
edn_csr_rw 0.980s 15.124us 20 20 100.00
edn_csr_aliasing 1.610s 67.437us 5 5 100.00
edn_same_csr_outstanding 1.480s 295.714us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.000s 27.828us 5 5 100.00
edn_csr_rw 0.980s 15.124us 20 20 100.00
edn_csr_aliasing 1.610s 67.437us 5 5 100.00
edn_same_csr_outstanding 1.480s 295.714us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 1.387m 11.140ms 4 5 80.00
edn_tl_intg_err 2.770s 107.972us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.030s 17.838us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.700s 362.134us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 1.387m 11.140ms 4 5 80.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 1.387m 11.140ms 4 5 80.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 1.387m 11.140ms 4 5 80.00
V2S sec_cm_ctr_redun edn_sec_cm 1.387m 11.140ms 4 5 80.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.700s 362.134us 200 200 100.00
edn_sec_cm 1.387m 11.140ms 4 5 80.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.700s 362.134us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 2.770s 107.972us 20 20 100.00
V2S TOTAL 34 35 97.14
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 50.979m 261.434ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 1129 1130 99.91

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 3 3 2 66.67
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.67 98.25 93.73 97.02 92.44 96.37 99.77 92.08

Failure Buckets

Past Results