EDN Simulation Results

Wednesday July 03 2024 23:02:32 UTC

GitHub Revision: e6706fcc7b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 8083624550445280117614176890238357255195852125596561370221115831648066795492

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.080s 16.929us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.010s 16.980us 5 5 100.00
V1 csr_rw edn_csr_rw 1.040s 24.513us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 6.210s 251.180us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.560s 36.908us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.050s 277.068us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.040s 24.513us 20 20 100.00
edn_csr_aliasing 1.560s 36.908us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 5.476m 10.007ms 299 300 99.67
V2 csrng_commands edn_genbits 5.476m 10.007ms 299 300 99.67
V2 genbits edn_genbits 5.476m 10.007ms 299 300 99.67
V2 interrupts edn_intr 1.170s 30.286us 50 50 100.00
V2 alerts edn_alert 1.630s 414.415us 200 200 100.00
V2 errs edn_err 1.400s 27.821us 100 100 100.00
V2 disable edn_disable 0.990s 165.405us 50 50 100.00
edn_disable_auto_req_mode 1.430s 42.913us 50 50 100.00
V2 stress_all edn_stress_all 8.350s 425.268us 50 50 100.00
V2 intr_test edn_intr_test 0.970s 16.573us 50 50 100.00
V2 alert_test edn_alert_test 1.230s 76.339us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.680s 227.203us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.680s 227.203us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.010s 16.980us 5 5 100.00
edn_csr_rw 1.040s 24.513us 20 20 100.00
edn_csr_aliasing 1.560s 36.908us 5 5 100.00
edn_same_csr_outstanding 1.540s 74.389us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.010s 16.980us 5 5 100.00
edn_csr_rw 1.040s 24.513us 20 20 100.00
edn_csr_aliasing 1.560s 36.908us 5 5 100.00
edn_same_csr_outstanding 1.540s 74.389us 20 20 100.00
V2 TOTAL 939 940 99.89
V2S tl_intg_err edn_sec_cm 9.350s 1.885ms 5 5 100.00
edn_tl_intg_err 5.210s 619.392us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.000s 31.762us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.630s 414.415us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 9.350s 1.885ms 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 9.350s 1.885ms 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 9.350s 1.885ms 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 9.350s 1.885ms 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.630s 414.415us 200 200 100.00
edn_sec_cm 9.350s 1.885ms 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.630s 414.415us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 5.210s 619.392us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 42.725m 334.628ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 1129 1130 99.91

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 10 90.91
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.87 98.25 93.91 97.07 93.60 96.37 99.77 92.08

Failure Buckets

Past Results