EDN Simulation Results

Thursday July 04 2024 23:02:28 UTC

GitHub Revision: 3e678c112b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 94940390549829454688103081328166376218078465228811124044523808815554354133843

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.120s 17.417us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.990s 20.887us 5 5 100.00
V1 csr_rw edn_csr_rw 0.980s 14.407us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 6.850s 1.001ms 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.790s 88.407us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.160s 32.424us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.980s 14.407us 20 20 100.00
edn_csr_aliasing 1.790s 88.407us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 4.790s 617.425us 300 300 100.00
V2 csrng_commands edn_genbits 4.790s 617.425us 300 300 100.00
V2 genbits edn_genbits 4.790s 617.425us 300 300 100.00
V2 interrupts edn_intr 1.240s 22.854us 50 50 100.00
V2 alerts edn_alert 1.450s 296.373us 200 200 100.00
V2 errs edn_err 1.550s 36.416us 100 100 100.00
V2 disable edn_disable 0.980s 14.233us 50 50 100.00
edn_disable_auto_req_mode 1.530s 47.077us 50 50 100.00
V2 stress_all edn_stress_all 6.180s 2.295ms 50 50 100.00
V2 intr_test edn_intr_test 0.960s 13.926us 50 50 100.00
V2 alert_test edn_alert_test 1.420s 103.087us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.760s 178.292us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.760s 178.292us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.990s 20.887us 5 5 100.00
edn_csr_rw 0.980s 14.407us 20 20 100.00
edn_csr_aliasing 1.790s 88.407us 5 5 100.00
edn_same_csr_outstanding 1.510s 94.030us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.990s 20.887us 5 5 100.00
edn_csr_rw 0.980s 14.407us 20 20 100.00
edn_csr_aliasing 1.790s 88.407us 5 5 100.00
edn_same_csr_outstanding 1.510s 94.030us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 7.940s 1.046ms 5 5 100.00
edn_tl_intg_err 20.490s 1.312ms 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.040s 29.454us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.450s 296.373us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 7.940s 1.046ms 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 7.940s 1.046ms 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 7.940s 1.046ms 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 7.940s 1.046ms 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.450s 296.373us 200 200 100.00
edn_sec_cm 7.940s 1.046ms 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.450s 296.373us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 20.490s 1.312ms 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 52.725m 395.596ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 1130 1130 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.53 98.25 93.91 97.02 91.28 96.37 99.77 92.08

Past Results