EDN Simulation Results

Friday July 05 2024 23:02:55 UTC

GitHub Revision: 9edf84e236

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 47623749544922802985321435118963335754001495105472137721881337469861493653463

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.080s 17.703us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.970s 24.975us 5 5 100.00
V1 csr_rw edn_csr_rw 1.010s 19.743us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 6.520s 558.210us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.440s 34.600us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.210s 42.146us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.010s 19.743us 20 20 100.00
edn_csr_aliasing 1.440s 34.600us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 2.452m 12.169ms 300 300 100.00
V2 csrng_commands edn_genbits 2.452m 12.169ms 300 300 100.00
V2 genbits edn_genbits 2.452m 12.169ms 300 300 100.00
V2 interrupts edn_intr 1.250s 21.391us 50 50 100.00
V2 alerts edn_alert 1.500s 404.499us 200 200 100.00
V2 errs edn_err 1.370s 19.862us 100 100 100.00
V2 disable edn_disable 1.010s 33.249us 50 50 100.00
edn_disable_auto_req_mode 1.520s 46.721us 50 50 100.00
V2 stress_all edn_stress_all 6.510s 301.411us 50 50 100.00
V2 intr_test edn_intr_test 0.960s 25.530us 50 50 100.00
V2 alert_test edn_alert_test 1.800s 71.045us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 5.050s 853.633us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 5.050s 853.633us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.970s 24.975us 5 5 100.00
edn_csr_rw 1.010s 19.743us 20 20 100.00
edn_csr_aliasing 1.440s 34.600us 5 5 100.00
edn_same_csr_outstanding 1.430s 265.132us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.970s 24.975us 5 5 100.00
edn_csr_rw 1.010s 19.743us 20 20 100.00
edn_csr_aliasing 1.440s 34.600us 5 5 100.00
edn_same_csr_outstanding 1.430s 265.132us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 8.590s 990.647us 5 5 100.00
edn_tl_intg_err 3.080s 141.161us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.060s 17.868us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.500s 404.499us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 8.590s 990.647us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 8.590s 990.647us 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 8.590s 990.647us 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 8.590s 990.647us 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.500s 404.499us 200 200 100.00
edn_sec_cm 8.590s 990.647us 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.500s 404.499us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 3.080s 141.161us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 50.528m 232.762ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 1130 1130 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.53 98.25 93.91 97.07 91.28 96.37 99.77 92.08

Past Results