EDN Simulation Results

Saturday July 06 2024 23:02:28 UTC

GitHub Revision: c42c47ec2d

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3200059823452722292543998130245428086525417237473114929151723951411399280153

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.090s 20.095us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.960s 47.743us 5 5 100.00
V1 csr_rw edn_csr_rw 0.950s 15.026us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 5.090s 697.782us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.510s 156.258us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.930s 31.918us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.950s 15.026us 20 20 100.00
edn_csr_aliasing 1.510s 156.258us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 2.242m 10.450ms 300 300 100.00
V2 csrng_commands edn_genbits 2.242m 10.450ms 300 300 100.00
V2 genbits edn_genbits 2.242m 10.450ms 300 300 100.00
V2 interrupts edn_intr 1.260s 22.670us 50 50 100.00
V2 alerts edn_alert 1.470s 30.313us 200 200 100.00
V2 errs edn_err 1.300s 42.212us 100 100 100.00
V2 disable edn_disable 0.970s 13.089us 50 50 100.00
edn_disable_auto_req_mode 1.370s 41.292us 50 50 100.00
V2 stress_all edn_stress_all 7.210s 396.457us 50 50 100.00
V2 intr_test edn_intr_test 0.990s 18.882us 50 50 100.00
V2 alert_test edn_alert_test 1.690s 68.454us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.720s 562.440us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.720s 562.440us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.960s 47.743us 5 5 100.00
edn_csr_rw 0.950s 15.026us 20 20 100.00
edn_csr_aliasing 1.510s 156.258us 5 5 100.00
edn_same_csr_outstanding 1.490s 273.718us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.960s 47.743us 5 5 100.00
edn_csr_rw 0.950s 15.026us 20 20 100.00
edn_csr_aliasing 1.510s 156.258us 5 5 100.00
edn_same_csr_outstanding 1.490s 273.718us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 8.530s 1.000ms 5 5 100.00
edn_tl_intg_err 3.110s 123.358us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.010s 21.273us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.470s 30.313us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 8.530s 1.000ms 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 8.530s 1.000ms 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 8.530s 1.000ms 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 8.530s 1.000ms 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.470s 30.313us 200 200 100.00
edn_sec_cm 8.530s 1.000ms 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.470s 30.313us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 3.110s 123.358us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 50.665m 1.051s 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 1130 1130 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.65 98.25 93.97 97.02 91.86 96.37 99.77 92.28

Past Results