EDN Simulation Results

Sunday July 07 2024 23:02:38 UTC

GitHub Revision: 2e5d86c9b5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75221189197949424635294305394615322888112457483844341597147780944629972574676

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.030s 83.027us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.030s 33.029us 5 5 100.00
V1 csr_rw edn_csr_rw 1.000s 58.909us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 6.440s 1.380ms 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.230s 24.998us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.790s 26.501us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.000s 58.909us 20 20 100.00
edn_csr_aliasing 1.230s 24.998us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 5.350s 489.202us 300 300 100.00
V2 csrng_commands edn_genbits 5.350s 489.202us 300 300 100.00
V2 genbits edn_genbits 5.350s 489.202us 300 300 100.00
V2 interrupts edn_intr 1.210s 22.109us 50 50 100.00
V2 alerts edn_alert 1.560s 230.628us 200 200 100.00
V2 errs edn_err 1.450s 27.948us 100 100 100.00
V2 disable edn_disable 1.020s 14.450us 50 50 100.00
edn_disable_auto_req_mode 1.440s 38.054us 50 50 100.00
V2 stress_all edn_stress_all 6.300s 326.040us 50 50 100.00
V2 intr_test edn_intr_test 0.990s 17.730us 50 50 100.00
V2 alert_test edn_alert_test 1.280s 85.063us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.010s 106.301us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.010s 106.301us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.030s 33.029us 5 5 100.00
edn_csr_rw 1.000s 58.909us 20 20 100.00
edn_csr_aliasing 1.230s 24.998us 5 5 100.00
edn_same_csr_outstanding 1.570s 43.578us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.030s 33.029us 5 5 100.00
edn_csr_rw 1.000s 58.909us 20 20 100.00
edn_csr_aliasing 1.230s 24.998us 5 5 100.00
edn_same_csr_outstanding 1.570s 43.578us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 9.540s 1.270ms 5 5 100.00
edn_tl_intg_err 2.860s 463.489us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.030s 19.422us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.560s 230.628us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 9.540s 1.270ms 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 9.540s 1.270ms 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 9.540s 1.270ms 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 9.540s 1.270ms 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.560s 230.628us 200 200 100.00
edn_sec_cm 9.540s 1.270ms 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.560s 230.628us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 2.860s 463.489us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 52.185m 288.164ms 49 50 98.00
V3 TOTAL 49 50 98.00
TOTAL 1129 1130 99.91

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.78 98.25 93.97 97.02 93.02 96.37 99.77 92.08

Failure Buckets

Past Results