EDN Simulation Results

Tuesday July 09 2024 23:02:48 UTC

GitHub Revision: 6a84251492

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 61727890964832844865465694323650730626175387240181955975848876152363892893427

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.100s 19.855us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.930s 21.872us 5 5 100.00
V1 csr_rw edn_csr_rw 0.950s 58.399us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 6.430s 509.345us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.560s 106.562us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.860s 28.543us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.950s 58.399us 20 20 100.00
edn_csr_aliasing 1.560s 106.562us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 5.550s 824.907us 300 300 100.00
V2 csrng_commands edn_genbits 5.550s 824.907us 300 300 100.00
V2 genbits edn_genbits 5.550s 824.907us 300 300 100.00
V2 interrupts edn_intr 1.180s 22.395us 50 50 100.00
V2 alerts edn_alert 1.470s 307.856us 200 200 100.00
V2 errs edn_err 1.320s 27.691us 100 100 100.00
V2 disable edn_disable 1.100s 14.112us 50 50 100.00
edn_disable_auto_req_mode 1.470s 96.471us 50 50 100.00
V2 stress_all edn_stress_all 6.750s 339.343us 50 50 100.00
V2 intr_test edn_intr_test 1.010s 18.078us 50 50 100.00
V2 alert_test edn_alert_test 1.120s 22.966us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 5.200s 306.109us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 5.200s 306.109us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.930s 21.872us 5 5 100.00
edn_csr_rw 0.950s 58.399us 20 20 100.00
edn_csr_aliasing 1.560s 106.562us 5 5 100.00
edn_same_csr_outstanding 1.520s 113.703us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.930s 21.872us 5 5 100.00
edn_csr_rw 0.950s 58.399us 20 20 100.00
edn_csr_aliasing 1.560s 106.562us 5 5 100.00
edn_same_csr_outstanding 1.520s 113.703us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 9.640s 664.196us 5 5 100.00
edn_tl_intg_err 2.940s 121.608us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.090s 21.273us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.470s 307.856us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 9.640s 664.196us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 9.640s 664.196us 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 9.640s 664.196us 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 9.640s 664.196us 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.470s 307.856us 200 200 100.00
edn_sec_cm 9.640s 664.196us 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.470s 307.856us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 2.940s 121.608us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 42.876m 212.158ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 1130 1130 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.78 98.25 93.91 97.02 93.02 96.37 99.77 92.08

Past Results