EDN Simulation Results

Wednesday July 10 2024 23:02:26 UTC

GitHub Revision: 39211701b5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 52262812535389540465251148247405743574935129745685597413714598750252192397067

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.110s 19.766us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.990s 28.370us 5 5 100.00
V1 csr_rw edn_csr_rw 1.030s 17.993us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 5.400s 675.973us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.570s 125.131us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.690s 68.456us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.030s 17.993us 20 20 100.00
edn_csr_aliasing 1.570s 125.131us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 1.178m 2.234ms 300 300 100.00
V2 csrng_commands edn_genbits 1.178m 2.234ms 300 300 100.00
V2 genbits edn_genbits 1.178m 2.234ms 300 300 100.00
V2 interrupts edn_intr 1.170s 21.508us 50 50 100.00
V2 alerts edn_alert 1.410s 33.906us 200 200 100.00
V2 errs edn_err 1.440s 37.581us 100 100 100.00
V2 disable edn_disable 0.950s 14.992us 50 50 100.00
edn_disable_auto_req_mode 1.440s 41.867us 50 50 100.00
V2 stress_all edn_stress_all 8.350s 414.285us 50 50 100.00
V2 intr_test edn_intr_test 0.970s 18.324us 50 50 100.00
V2 alert_test edn_alert_test 1.200s 46.902us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.080s 106.483us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.080s 106.483us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.990s 28.370us 5 5 100.00
edn_csr_rw 1.030s 17.993us 20 20 100.00
edn_csr_aliasing 1.570s 125.131us 5 5 100.00
edn_same_csr_outstanding 1.460s 107.186us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.990s 28.370us 5 5 100.00
edn_csr_rw 1.030s 17.993us 20 20 100.00
edn_csr_aliasing 1.570s 125.131us 5 5 100.00
edn_same_csr_outstanding 1.460s 107.186us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 7.930s 913.367us 5 5 100.00
edn_tl_intg_err 2.830s 427.990us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.060s 28.851us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.410s 33.906us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 7.930s 913.367us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 7.930s 913.367us 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 7.930s 913.367us 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 7.930s 913.367us 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.410s 33.906us 200 200 100.00
edn_sec_cm 7.930s 913.367us 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.410s 33.906us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 2.830s 427.990us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 42.216m 99.318ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 1130 1130 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.60 98.25 93.85 97.02 91.86 96.37 99.77 92.08

Past Results