EDN Simulation Results

Thursday July 11 2024 23:02:31 UTC

GitHub Revision: edf2fd5092

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 110991919330983905489672005724934609038320729526710604109871030362225161447318

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.070s 18.518us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.920s 29.603us 5 5 100.00
V1 csr_rw edn_csr_rw 0.980s 18.357us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 7.110s 1.318ms 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.580s 39.026us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.770s 30.863us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.980s 18.357us 20 20 100.00
edn_csr_aliasing 1.580s 39.026us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 1.040m 2.309ms 300 300 100.00
V2 csrng_commands edn_genbits 1.040m 2.309ms 300 300 100.00
V2 genbits edn_genbits 1.040m 2.309ms 300 300 100.00
V2 interrupts edn_intr 1.270s 22.435us 50 50 100.00
V2 alerts edn_alert 1.480s 302.810us 200 200 100.00
V2 errs edn_err 1.450s 34.576us 100 100 100.00
V2 disable edn_disable 0.980s 19.973us 50 50 100.00
edn_disable_auto_req_mode 1.380s 69.226us 50 50 100.00
V2 stress_all edn_stress_all 7.190s 370.902us 50 50 100.00
V2 intr_test edn_intr_test 1.030s 19.434us 50 50 100.00
V2 alert_test edn_alert_test 1.440s 47.864us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 3.800s 112.317us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 3.800s 112.317us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.920s 29.603us 5 5 100.00
edn_csr_rw 0.980s 18.357us 20 20 100.00
edn_csr_aliasing 1.580s 39.026us 5 5 100.00
edn_same_csr_outstanding 1.460s 35.408us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.920s 29.603us 5 5 100.00
edn_csr_rw 0.980s 18.357us 20 20 100.00
edn_csr_aliasing 1.580s 39.026us 5 5 100.00
edn_same_csr_outstanding 1.460s 35.408us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 4.640s 478.740us 5 5 100.00
edn_tl_intg_err 6.200s 372.625us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.120s 17.884us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.480s 302.810us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 4.640s 478.740us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 4.640s 478.740us 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 4.640s 478.740us 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 4.640s 478.740us 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.480s 302.810us 200 200 100.00
edn_sec_cm 4.640s 478.740us 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.480s 302.810us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 6.200s 372.625us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 51.466m 335.096ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 1130 1130 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.55 98.25 93.91 97.02 91.28 96.37 99.77 92.28

Past Results