EDN Simulation Results

Friday July 12 2024 23:02:19 UTC

GitHub Revision: 5967df933a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 46476530947956470787268850137993439884379231200278174763551439909664842175844

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.080s 23.239us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.020s 17.868us 5 5 100.00
V1 csr_rw edn_csr_rw 0.980s 14.541us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 3.590s 261.509us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.430s 68.010us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.070s 30.990us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.980s 14.541us 20 20 100.00
edn_csr_aliasing 1.430s 68.010us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 1.240m 2.303ms 300 300 100.00
V2 csrng_commands edn_genbits 1.240m 2.303ms 300 300 100.00
V2 genbits edn_genbits 1.240m 2.303ms 300 300 100.00
V2 interrupts edn_intr 1.350s 35.014us 50 50 100.00
V2 alerts edn_alert 1.500s 301.387us 200 200 100.00
V2 errs edn_err 1.710s 33.831us 100 100 100.00
V2 disable edn_disable 0.960s 34.233us 50 50 100.00
edn_disable_auto_req_mode 1.650s 54.402us 50 50 100.00
V2 stress_all edn_stress_all 6.370s 600.009us 50 50 100.00
V2 intr_test edn_intr_test 1.000s 16.669us 50 50 100.00
V2 alert_test edn_alert_test 1.450s 49.329us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.700s 521.072us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.700s 521.072us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.020s 17.868us 5 5 100.00
edn_csr_rw 0.980s 14.541us 20 20 100.00
edn_csr_aliasing 1.430s 68.010us 5 5 100.00
edn_same_csr_outstanding 1.540s 38.645us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.020s 17.868us 5 5 100.00
edn_csr_rw 0.980s 14.541us 20 20 100.00
edn_csr_aliasing 1.430s 68.010us 5 5 100.00
edn_same_csr_outstanding 1.540s 38.645us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 20.350s 1.391ms 5 5 100.00
edn_tl_intg_err 13.550s 3.552ms 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 0.990s 35.223us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.500s 301.387us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 20.350s 1.391ms 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 20.350s 1.391ms 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 20.350s 1.391ms 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 20.350s 1.391ms 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.500s 301.387us 200 200 100.00
edn_sec_cm 20.350s 1.391ms 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.500s 301.387us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 13.550s 3.552ms 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 41.908m 626.028ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 1130 1130 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.84 98.25 93.97 97.02 93.60 96.37 99.77 91.89

Past Results