EDN Simulation Results

Saturday July 13 2024 23:02:33 UTC

GitHub Revision: d51405297e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 101086804359139103922259090811397817605469534164678958852189348539757618502888

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.330s 38.330us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.970s 57.452us 5 5 100.00
V1 csr_rw edn_csr_rw 0.980s 63.574us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 3.370s 159.047us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.500s 138.240us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.240s 55.690us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.980s 63.574us 20 20 100.00
edn_csr_aliasing 1.500s 138.240us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 4.170s 278.368us 300 300 100.00
V2 csrng_commands edn_genbits 4.170s 278.368us 300 300 100.00
V2 genbits edn_genbits 4.170s 278.368us 300 300 100.00
V2 interrupts edn_intr 1.270s 25.978us 50 50 100.00
V2 alerts edn_alert 1.420s 40.584us 200 200 100.00
V2 errs edn_err 1.360s 24.494us 100 100 100.00
V2 disable edn_disable 1.120s 21.129us 50 50 100.00
edn_disable_auto_req_mode 1.840s 56.461us 50 50 100.00
V2 stress_all edn_stress_all 6.830s 373.216us 50 50 100.00
V2 intr_test edn_intr_test 0.970s 16.265us 50 50 100.00
V2 alert_test edn_alert_test 1.080s 15.227us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 5.220s 611.578us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 5.220s 611.578us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.970s 57.452us 5 5 100.00
edn_csr_rw 0.980s 63.574us 20 20 100.00
edn_csr_aliasing 1.500s 138.240us 5 5 100.00
edn_same_csr_outstanding 1.530s 70.989us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.970s 57.452us 5 5 100.00
edn_csr_rw 0.980s 63.574us 20 20 100.00
edn_csr_aliasing 1.500s 138.240us 5 5 100.00
edn_same_csr_outstanding 1.530s 70.989us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 8.550s 1.955ms 5 5 100.00
edn_tl_intg_err 2.720s 211.981us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.040s 18.648us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.420s 40.584us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 8.550s 1.955ms 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 8.550s 1.955ms 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 8.550s 1.955ms 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 8.550s 1.955ms 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.420s 40.584us 200 200 100.00
edn_sec_cm 8.550s 1.955ms 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.420s 40.584us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 2.720s 211.981us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 51.787m 553.902ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 1130 1130 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
94.73 98.25 93.97 91.35 91.28 96.37 99.77 92.08

Past Results