EDN Simulation Results

Sunday July 14 2024 23:02:31 UTC

GitHub Revision: c04cc5d074

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 63544391231451201456762274895161998707503467555380647510071702152169450996489

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.040s 16.854us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.020s 18.974us 5 5 100.00
V1 csr_rw edn_csr_rw 0.970s 15.553us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 6.360s 252.687us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.580s 64.028us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.260s 33.247us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.970s 15.553us 20 20 100.00
edn_csr_aliasing 1.580s 64.028us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 4.630s 430.947us 300 300 100.00
V2 csrng_commands edn_genbits 4.630s 430.947us 300 300 100.00
V2 genbits edn_genbits 4.630s 430.947us 300 300 100.00
V2 interrupts edn_intr 1.250s 20.977us 50 50 100.00
V2 alerts edn_alert 1.460s 32.266us 200 200 100.00
V2 errs edn_err 1.390s 58.905us 100 100 100.00
V2 disable edn_disable 1.030s 13.934us 50 50 100.00
edn_disable_auto_req_mode 1.560s 41.045us 50 50 100.00
V2 stress_all edn_stress_all 7.430s 403.367us 50 50 100.00
V2 intr_test edn_intr_test 0.930s 44.593us 50 50 100.00
V2 alert_test edn_alert_test 1.110s 30.137us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 5.080s 314.730us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 5.080s 314.730us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.020s 18.974us 5 5 100.00
edn_csr_rw 0.970s 15.553us 20 20 100.00
edn_csr_aliasing 1.580s 64.028us 5 5 100.00
edn_same_csr_outstanding 1.470s 428.008us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.020s 18.974us 5 5 100.00
edn_csr_rw 0.970s 15.553us 20 20 100.00
edn_csr_aliasing 1.580s 64.028us 5 5 100.00
edn_same_csr_outstanding 1.470s 428.008us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 8.730s 967.064us 5 5 100.00
edn_tl_intg_err 3.540s 169.053us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.030s 16.449us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.460s 32.266us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 8.730s 967.064us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 8.730s 967.064us 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 8.730s 967.064us 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 8.730s 967.064us 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.460s 32.266us 200 200 100.00
edn_sec_cm 8.730s 967.064us 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.460s 32.266us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 3.540s 169.053us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 44.061m 211.229ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 1130 1130 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.73 98.25 93.97 97.02 92.44 96.37 99.77 92.28

Past Results