EDN Simulation Results

Monday July 15 2024 23:02:37 UTC

GitHub Revision: a04e34f557

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 78455839157994684327892029952813991699715169368132023215715425571513813941951

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.040s 17.549us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.920s 12.203us 5 5 100.00
V1 csr_rw edn_csr_rw 0.950s 16.609us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 5.220s 182.416us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.610s 151.604us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.980s 109.425us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.950s 16.609us 20 20 100.00
edn_csr_aliasing 1.610s 151.604us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 1.199m 2.186ms 300 300 100.00
V2 csrng_commands edn_genbits 1.199m 2.186ms 300 300 100.00
V2 genbits edn_genbits 1.199m 2.186ms 300 300 100.00
V2 interrupts edn_intr 1.240s 21.226us 50 50 100.00
V2 alerts edn_alert 1.410s 192.399us 200 200 100.00
V2 errs edn_err 1.340s 33.001us 100 100 100.00
V2 disable edn_disable 0.950s 12.422us 50 50 100.00
edn_disable_auto_req_mode 1.530s 50.216us 50 50 100.00
V2 stress_all edn_stress_all 6.480s 721.038us 50 50 100.00
V2 intr_test edn_intr_test 0.990s 16.243us 50 50 100.00
V2 alert_test edn_alert_test 1.260s 38.309us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.230s 290.845us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.230s 290.845us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.920s 12.203us 5 5 100.00
edn_csr_rw 0.950s 16.609us 20 20 100.00
edn_csr_aliasing 1.610s 151.604us 5 5 100.00
edn_same_csr_outstanding 1.470s 39.811us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.920s 12.203us 5 5 100.00
edn_csr_rw 0.950s 16.609us 20 20 100.00
edn_csr_aliasing 1.610s 151.604us 5 5 100.00
edn_same_csr_outstanding 1.470s 39.811us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 8.140s 2.963ms 5 5 100.00
edn_tl_intg_err 4.300s 456.554us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.020s 30.072us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.410s 192.399us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 8.140s 2.963ms 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 8.140s 2.963ms 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 8.140s 2.963ms 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 8.140s 2.963ms 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.410s 192.399us 200 200 100.00
edn_sec_cm 8.140s 2.963ms 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.410s 192.399us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 4.300s 456.554us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 57.276m 537.503ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 1130 1130 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.78 98.25 93.91 97.02 93.02 96.37 99.77 92.08

Past Results