EDN Simulation Results

Tuesday July 16 2024 23:15:02 UTC

GitHub Revision: aad711e1bc

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 38297581588405771015102977205739484163575733999253050480227719508149669635625

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.050s 20.089us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.990s 67.134us 5 5 100.00
V1 csr_rw edn_csr_rw 0.970s 144.288us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 6.270s 250.989us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.720s 59.000us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.150s 108.797us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.970s 144.288us 20 20 100.00
edn_csr_aliasing 1.720s 59.000us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 7.070s 701.754us 300 300 100.00
V2 csrng_commands edn_genbits 7.070s 701.754us 300 300 100.00
V2 genbits edn_genbits 7.070s 701.754us 300 300 100.00
V2 interrupts edn_intr 1.330s 31.867us 50 50 100.00
V2 alerts edn_alert 1.460s 199.215us 200 200 100.00
V2 errs edn_err 1.340s 30.135us 100 100 100.00
V2 disable edn_disable 0.970s 13.773us 50 50 100.00
edn_disable_auto_req_mode 1.570s 45.328us 50 50 100.00
V2 stress_all edn_stress_all 7.850s 415.249us 50 50 100.00
V2 intr_test edn_intr_test 1.000s 17.068us 50 50 100.00
V2 alert_test edn_alert_test 1.880s 287.869us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.360s 259.434us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.360s 259.434us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.990s 67.134us 5 5 100.00
edn_csr_rw 0.970s 144.288us 20 20 100.00
edn_csr_aliasing 1.720s 59.000us 5 5 100.00
edn_same_csr_outstanding 1.490s 139.974us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.990s 67.134us 5 5 100.00
edn_csr_rw 0.970s 144.288us 20 20 100.00
edn_csr_aliasing 1.720s 59.000us 5 5 100.00
edn_same_csr_outstanding 1.490s 139.974us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 10.380s 722.156us 5 5 100.00
edn_tl_intg_err 5.050s 276.633us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.030s 17.880us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.460s 199.215us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 10.380s 722.156us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 10.380s 722.156us 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 10.380s 722.156us 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 10.380s 722.156us 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.460s 199.215us 200 200 100.00
edn_sec_cm 10.380s 722.156us 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.460s 199.215us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 5.050s 276.633us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 47.869m 126.875ms 49 50 98.00
V3 TOTAL 49 50 98.00
TOTAL 1129 1130 99.91

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.60 98.25 93.91 96.97 91.86 96.37 99.77 92.08

Failure Buckets

Past Results